ram_top.v

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`timescale 1ns/1ps
module ram_top;
reg clk,rst;
wire [3:0] q;

always #10 clk=~clk;

initial 
	begin
		clk=0;rst=1;
		#50 rst<=0;
		#50 rst<=1;
	end
										
ram_control ram_control(.clk(clk),.rst(rst),.q(q));
endmodule