outputs_icc.tcl

synopsys icc 使用参考脚本

## ICC RM Version: B-2008.09        


#######################################
####Outputs Script
#######################################


source -echo icc_setup.tcl


##Open Design
open_mw_lib $MW_DESIGN_LIBRARY

if {![file exists [which $PT_DIR/pt_shell]] } {
  open_mw_cel $ICC_CHIP_FINISH_CEL
} else {
  open_mw_cel $ICC_SIGNOFF_OPT_CEL
}

link



##Change Names
change_names -rules verilog -hierarchy




##Verilog
set_app_var verilogout_no_tri true
write_verilog                                   $RESULTS_DIR/$DESIGN_NAME.output.v
write_verilog -pg_ports -output_net_name_for_pg $RESULTS_DIR/$DESIGN_NAME.output.pg.v




##SDC
set_app_var write_sdc_output_lumped_net_capacitance false
set_app_var write_sdc_output_net_resistance false
write_sdc $RESULTS_DIR/$DESIGN_NAME.output.sdc




##Parasitics
extract_rc -coupling_cap
#write_parasitics  -format SPEF -output $RESULTS_DIR/$DESIGN_NAME.output.spef
write_parasitics  -format SBPF -output $RESULTS_DIR/$DESIGN_NAME.output.sbpf




##DEF
write_def -output  $RESULTS_DIR/$DESIGN_NAME.output.def




###GDSII
##Set options - usually also include a mapping file (-map_layer)
# set_write_stream_options \
#       -child_depth 99 \
#       -output_filling fill \
#       -output_outdated_fill \
#       -output_pin geometry \
#       -keep_data_type
# write_stream -lib_name $MW_DESIGN_LIBRARY -format gds $RESULTS_DIR/$DESIGN_NAME.gds




if {$ICC_CREATE_MODEL } {


  save_mw_cel -as $DESIGN_NAME
  close_mw_cel
  open_mw_cel $DESIGN_NAME
  create_ilm -include_xtalk 
  
  ##create FRAM
  create_macro_fram
  

  ##create Antenna Info
  if {$ICC_FIX_ANTENNA} {

      set_droute_options -name doAntennaConx -value 4
      extract_hier_antenna_property -cell_name $DESIGN_NAME

  }

  close_mw_cel 
}




exit