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📄 common_cts_settings_icc.tcl

📁 synopsys icc 使用参考脚本
💻 TCL
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## ICC RM Version: B-2008.09        echo "\tLoading :\t\t [which [info script]]"## CTS Common Session Options - set in place_opt and clock_opt sessions## Best Practices - User must set or comment out## Clock Tree References## Choose Balanced Buffers and Inverters for best results## Avoid low strengths for initial CTS (bad CTS)## Avoid high strengths for signal EM problems## Each of the following take a space separated list of buffers/cels: ex: "buf1 inv1 inv2"if {$ICC_CTS_REF_LIST != ""} {set_clock_tree_references -references $ICC_CTS_REF_LIST}if {$ICC_CTS_REF_DEL_INS_ONLY != ""} {set_clock_tree_references -delay_insertion_only -references $ICC_CTS_REF_DEL_INS_ONLY}if {$ICC_CTS_REF_SIZING_ONLY != ""} {set_clock_tree_references -sizing_only -references $ICC_CTS_REF_SIZING_ONLY}## CLOCK NDR's## Specify the rule prior to CTS so that CTS can predict its effects## Avoid setting the rule on metal 1 - avoids pin access issues on ## buffers and gates in the tree# set ICC_CTS_RULE_NAME "my_clock_routing_rule"## Create Clock NDR - only if it hasn't been created yet - check if rule exists first#redirect -var x {report_routing_rules $ICC_CTS_RULE_NAME}#if {$ICC_CTS_RULE_NAME != "" && [regexp "Info: No nondrule" $x]} {# define_routing_rule $ICC_CTS_RULE_NAME -default_reference_rule \#       -spacings "BEST_PRACTICE_clock_ndr_metal_layer_and_spacing" \#       -widths "BEST_PRACTICE_clock_ndr_metal_layer_and_width" \#       -via_cuts "BEST_PRACTICE_clock_ndr_via_name_and_mXn_pairs"#report_routing_rule $ICC_CTS_RULE_NAME## at 65 nm, better SI protection if you put NDR on sink, provided you ## don't set the NDR on pin access layers## otherwise set -use_default_routeing_for_sinks to 1 to avoid NDR on ## clock sink## set_clock_tree_options -routing_rule $ICC_CTS_RULE_NAME -use_default_routing_for_sinks 1#}##Typically route clocks on metal3 and aboveif {$ICC_CTS_LAYER_LIST != ""} {set_clock_tree_options -layer_list $ICC_CTS_LAYER_LIST}## Inter Clock Delay Options ## Must also edit clock_opt_icc.tcl script and set -inter_clock_balance on the clock_opt -only_cts line# set_inter_clock_delay_options -balance_group <balance_group> -target_delay_clock <target_delay_clock> -target_delay_value <target_delay_value> -delay_offset <delay_offset> -offset_to <offset_to> -offset_from <offset_from>## End of CTS Optimization Sesssion Options #############

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