init_design_icc.tcl

synopsys icc 使用参考脚本

## ICC RM Version: B-2008.09 



##########################################################################################
## init_design_icc.tcl : initial scripts that reads the design, applies constraints and
##                   generates a zero interconnect timing report
##########################################################################################

source -echo icc_setup.tcl

########################################################################################
# Design Creation 
########################################################################################


if { $ICC_INIT_DESIGN_INPUT == "MW" } {


########################################################################################
# MW CEL as the format between DCT and ICC
########################################################################################

 open_mw_cel $ICC_INPUT_CEL -library $MW_DESIGN_LIBRARY 

}


if {$ICC_INIT_DESIGN_INPUT != "MW" } {

  if { ![file exists $MW_DESIGN_LIBRARY/lib] } {
     if { [file exists [which $MW_REFERENCE_CONTROL_FILE]]} {
       create_mw_lib \
            -tech $TECH_FILE \
            -bus_naming_style {[%d]} \
            -reference_control_file $MW_REFERENCE_CONTROL_FILE \
            $MW_DESIGN_LIBRARY 
     } else {
       create_mw_lib \
            -tech $TECH_FILE \
            -bus_naming_style {[%d]} \
            -mw_reference_library $MW_REFERENCE_LIB_DIRS \
            $MW_DESIGN_LIBRARY 
       }
  }

}


if {$ICC_INIT_DESIGN_INPUT == "DDC" } {


########################################################################################
# DDC as the format between DCT and ICC
########################################################################################

  open_mw_lib $MW_DESIGN_LIBRARY
  import_designs $ICC_IN_DDC_FILE -format ddc -top $DESIGN_NAME -cel $DESIGN_NAME

}


if {$ICC_INIT_DESIGN_INPUT == "VERILOG" } {


########################################################################################
# Ascii as the format between DCT and ICC
########################################################################################

    open_mw_lib $MW_DESIGN_LIBRARY

##     foreach VERILOG_FILE $ICC_IN_VERILOG_NETLIST_FILE {
##       echo "SCRIPT-Info: Reading $VERILOG_FILE"
##       ## add -dirty_netlist in case there are mismatches between the VERILOG netlist and the FRAM view of the cells
##       read_verilog_to_cel $VERILOG_FILE 
##     }
    read_verilog $ICC_IN_VERILOG_NETLIST_FILE 

    current_design $DESIGN_NAME

    uniquify_fp_mw_cel
    current_design $DESIGN_NAME
    link


  # non MCMM mode, i.e. just reading the one SDC
  if {!$MCMM_MODE } {

      read_sdc $ICC_IN_SDC_FILE 
      set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]]
      group_path -name REGOUT -to [all_outputs]
      group_path -name REGIN -from [remove_from_collection [all_inputs] $ports_clock_root]
      group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs]

  } 

  # MV settings for ascii flow
  if {$MV_MODE == "UPF"} {
      load_upf $ICC_IN_UPF_FILE 

  }

  if {$MV_MODE == "NONUPF"} {
      source -echo mv_setup_design.tcl   
  }

}

if { [check_error -verbose] != 0} { echo "SCRIPT-Error, flagging ..." }





########################################################################################
# As the design is loaded now, MCMM mode can be entered
########################################################################################
if {$MCMM_MODE} {

  echo "SCRIPT-Info : starting the MCMM flow" 
  remove_sdc
  remove_scenario -all
  source -echo $ICC_MCMM_SCENARIOS_FILE

}

if {!$MCMM_MODE } {
   remove_propagated_clock [all_clocks] 
} else {

   set_active_scenarios [lminus [all_scenarios] $ICC_MCMM_CTS_SCENARIO] 
   foreach scenario [all_active_scenarios] { 
     current_scenario $scenario 
     remove_propagated_clock [all_clocks]
   };

  }





## Unfixing the hard macros
if {[all_macro_cells] != "" } { remove_dont_touch_placement [all_macro_cells] }

#############################################################################################################################
# Floorplan Creation: DEF  OR  FLOORPLAN FILE  OR  TDF+initialize_floorplan
# CAUTION : Floorplan file flow with MV_MODE set to true is not currently supported by the scripts shown.
#############################################################################################################################




## Below steps apply if floorplan input is not a DEF file
##Connect P/G, to create Power and Ground Ports for Non-MV designs 
##Assuming P/G Ports are included in DEF file, need PG ports created for non-DEF flows 
if {$ICC_FLOORPLAN_INPUT != "DEF" && $MV_MODE == "NONE" } {


      ## If you have additional scripts to create pads, for example, create_cell, load it here       
      #       source $YOUR_SCRIPT 

      ## Connect PG first before loading floorplan file or initialize_floorplan
        if {[file exists [which $CUSTOM_CONNECT_PG_NETS_SCRIPT]]} {
        source -echo $CUSTOM_CONNECT_PG_NETS_SCRIPT
      } else {
	derive_pg_connection -power_net $MW_POWER_NET -power_pin $MW_POWER_PORT -ground_net $MW_GROUND_NET -ground_pin $MW_GROUND_PORT
      }

}



## You can have DEF, floorplan file, or TDF as floorplan input
if {$ICC_FLOORPLAN_INPUT == "DEF" } {

  if { [file exists [which $ICC_IN_DEF_FILE]]} {

        if { [file exists [which $ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE]]} {source $ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE}
        if { [file exists [which $ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE]]} {source $ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE}

	read_def -verbose -no_incremental -allow_physical $ICC_IN_DEF_FILE
        if { [check_error -verbose] != 0} { echo "SCRIPT-Error, flagging ..." }
  }


} elseif {$ICC_FLOORPLAN_INPUT == "FP_FILE" } {

  if { [file exists [which $ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE]]} {source $ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE}
  if { [file exists [which $ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE]]} {source $ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE}

  if { [file exists [which $ICC_IN_FLOORPLAN_FILE]]} {
	read_floorplan $ICC_IN_FLOORPLAN_FILE
  }


} elseif {$ICC_FLOORPLAN_INPUT == "CREATE"} {

  if { [file exists [which $ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE]]} {source $ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE}
  if { [file exists [which $ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE]]} {source $ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE}

  if {[file exists [which $ICC_IN_TDF_FILE]]} {
  	read_io_constraints $ICC_IN_TDF_FILE
  }
  
  initialize_floorplan \
  	-control_type aspect_ratio \
  	-core_aspect_ratio 1 \
  	-core_utilization 0.7 \
  	-row_core_ratio 1 \
  	-left_io2core 30 \
  	-bottom_io2core 30 \
  	-right_io2core 30 \
  	-top_io2core 30 \
  	-start_first_row

} elseif {$ICC_FLOORPLAN_INPUT == "USER_FILE"} {
   if {[file exists [which $ICC_IN_FLOORPLAN_USER_FILE]]} { source $ICC_IN_FLOORPLAN_USER_FILE}
} elseif {$ICC_FLOORPLAN_INPUT == "SKIP"} {
}


## If you want to add additional floorplan details such as macro location, corner cells, io filler cells, or pad rings, add them here, for example,
#	read_def -verbose -design $DESIGN_NAME -allow_physical $YOUR_INCREMENTAL_DEF_FILE
#	read_floorplan $YOUR_INCREMENTAL_FLOORPLAN_FILE
#	source $YOUR_SCRIPT






## TLU Plus Files
if {!$MCMM_MODE } {

   if {$TLUPLUS_MIN_FILE == ""} {set TLUPLUS_MIN_FILE $TLUPLUS_MAX_FILE}
   set_tlu_plus_files \
     -max_tluplus $TLUPLUS_MAX_FILE \
     -min_tluplus $TLUPLUS_MIN_FILE \
     -tech2itf_map $MAP_FILE               ;# set the tlu plus files

}



source -echo common_optimization_settings_icc.tcl
source -echo common_placement_settings_icc.tcl




if {$MV_MODE == "UPF"} {
                                            


########################################################################################
# MV mode : Creating the physical MV objects
########################################################################################

  derive_pg_connection -create_net 
  derive_pg_connection -reconnect 
  check_mv_design -power_nets -verbose

  report_power_domain
  report_voltage_area -all


}


if {$MV_MODE == "NONUPF"} {
                                            


########################################################################################
# MV mode : Creating the physical MV objects
########################################################################################

  report_power_domain
  report_voltage_area -all


}


if { $MV_MODE != "NONE" } {


  if { $ICC_DP_AUTO_CREATE_VA} { 

  ## Create VA with user specified locations; you'll need to provide exact coordinates
  if {$PD1 != "" } {create_voltage_area  -coordinate $VA1_COORDINATES -guard_band_x 1 -guard_band_y 1 -power_domain $PD1}
  if {$PD2 != "" } {create_voltage_area  -coordinate $VA2_COORDINATES -guard_band_x 1 -guard_band_y 1 -power_domain $PD2}
  if {$PD3 != "" } {create_voltage_area  -coordinate $VA3_COORDINATES -guard_band_x 1 -guard_band_y 1 -power_domain $PD3}
  if {$PD4 != "" } {create_voltage_area  -coordinate $VA4_COORDINATES -guard_band_x 1 -guard_band_y 1 -power_domain $PD4}
	
  } else {

  ## Create VA by tool automatically; you can provide desired utilization in the scripts below
  ## Location and shape of VA will be decided by the tool; you'll still need to make necessary adjustments  
  source -echo create_va_dp.tcl
 }

}


## Connect Power & Ground 

if {[file exists [which $CUSTOM_CONNECT_PG_NETS_SCRIPT]]} {
  source -echo $CUSTOM_CONNECT_PG_NETS_SCRIPT
} 


if {$MV_MODE == "UPF"} {
  source -echo mv_pg_connect.tcl 
} elseif {[file exists $CUSTOM_CONNECT_PG_NETS_SCRIPT]} {
   source -echo $CUSTOM_CONNECT_PG_NETS_SCRIPT   
} else {

derive_pg_connection -power_net $MW_POWER_NET -ground_net $MW_GROUND_NET -tie

}

#############################################
## MTCMOS CELL INSTANTIATION + CONNECTION  ##
#############################################

if {$MV_MODE == "NONUPF"} {


  ## If floorplan does not have switch cells instantiated in it, please use add_header_footer_cell_array command 
  ## as shown below BEFORE proceeding with daisy chain/hfn mode sleep net connectivity 
  ## using the command connect_power_switch 
  
  # create_voltage_area  -coordinate {238.230 71.150 278.200 104.725 } -name voltage_area_3 {u_start/u_carry/inst_u_126} -cycle_color
  # add_header_footer_cell_array -lib_cell "HEAD8M" -design "u_addsub"  -x_increment 50 -y_increment 50 -respect "all" -prefix "HF1_" -voltage_area "voltage_area_3" -bounding_box  {243 274 78 77}
  ## for daisy chain mode :
  # connect_power_switch -source enable -mode daisy -port_name enable_va_0 -ack_out ack -voltage_area voltage_area_2 -direction vertical
  ## for hfn mode :
  # connect_power_switch -source enable -mode hfn -port_name enable_va_0 -voltage_area voltage_area_2


}

if {$MV_MODE == "UPF" } {

  if { [file exists [which $CUSTOM_POWER_SWITCH_SCRIPT]] } {
    source -echo $CUSTOM_POWER_SWITCH_SCRIPT
  }

}



## Some checks specific for MV mode
if {$MV_MODE != "NONE"} {
  check_mv_design -verbose 
  if {$AO_MODE} {

    redirect -file $REPORTS_DIR/$DESIGN_NAME.ao_nets.rpt {get_always_on_logic -nets}
    redirect -file $REPORTS_DIR/$DESIGN_NAME.ao_all.rpt  {get_always_on_logic -all}
    redirect -file $REPORTS_DIR/$DESIGN_NAME.ao.rpt  {get_always_on_logic }
    ## optionally define an single_power or dual_power AO strategy for the different VA's
    # set_always_on_strategy -object_list {$PD2} -cell_type "single_power|dual_power"

  }

}

if {$MV_MODE == "UPF"} {
 save_upf $RESULTS_DIR/$ICC_FLOORPLAN_CEL.upf 
}




########################################################################################
# Saving the cell + snapshot creation
########################################################################################

create_qor_snapshot -name $ICC_FLOORPLAN_CEL -qor -timing -constraint 
save_mw_cel -as $ICC_FLOORPLAN_CEL
redirect -file $REPORTS_DIR/$ICC_FLOORPLAN_CEL.qor_snapshot.rpt {report_qor_snapshot}





########################################################################################
# Additional reporting: zero interconnect timing report and design summaries 
########################################################################################

redirect -file $REPORTS_DIR/$ICC_FLOORPLAN_CEL.sum {report_design -physical}

set_zero_interconnect_delay_mode true
redirect -file $REPORTS_DIR/$ICC_FLOORPLAN_CEL.zic.qor {report_qor}
set_zero_interconnect_delay_mode false


########################################################################################
# Checks : Library + technology checks
########################################################################################

## Add -rc_check <margin> to detect any big RC differences between the layers
redirect -file $REPORTS_DIR/check_physical_constraints.sum {check_physical_constraints -verbose}

set_check_library_options -all
redirect -file $REPORTS_DIR/check_library.sum {check_library}


exit