readme.icc-hrm.txt

synopsys icc 使用参考脚本

IC Compiler Hierarchical Reference Methodology README
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There are 3 stages in the IC Compiler Hierarchical Reference Methodology (RM) flow:
1. IC Compiler Design Planning performs hierarchical design planning based on virtual flat flow
2. IC Compiler performs block level implementation
3. IC Compiler performs top level implementation

Instructions to run IC Compiler Hierarchical RM:

STEP 0. Setup: Edit common_setup.tcl, icc_setup.tcl, Makefiles
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- common_setup.tcl: Common RM library and technology
* Make sure the path to your reference library and inputs are absolute paths.
  RM will set up sub-directories for your blocks and top-level design, and absolute paths are required for the sub-directories.
* In the example, a variable called $DESIGN_REF_DATA_PATH is used to manage the absolute paths to design data.
  This example shows how to specify absolute paths if you have a common root path for all your design data.

- icc_setup.tcl: IC Compiler specific options
* Important variables:
  ICC_DP_PLAN_GROUPS:    Provide the module instance names to be created into plan groups (future physical blocks).
                         IC Compiler will use this to create and arrange locations for the blocks automatically.
  ICC_DP_PLANGROUP_FILE: Specify the plan group dump file if you want to skip the auto-creation of plan groups.
                         The file should be generated by write_floorplan from your existing floorplan.
  If you do not provide information on which modules for block creation, IC Compiler will not have sufficient information, and the hierarchical flow will not work.
  ICC_DP_CTP_ANCHOR_CEL: If you would like to try clock planning, uncomment clock planning from the scripts and specify a buffer as the anchor cell.
			       IC Compiler requires the anchor cell to be specified for clock planning.

- Makefiles: Edit ICC_EXEC in Makefiles 


STEP 1. Hierarchical design planning: Run Makefile_hier from working directory: make -f Makefile_hier hier_dp &
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- This runs hierarchical partitioning all the way from reading netlist to commit.  At the end, it prepares block and top sub-directories.
- When it completes, sub-directories are prepared for your blocks and top-level design.
  Preparation includes: 
  - Creation of sub-directories, copying of scripts and necessary files, moving of libraries, setting up icc_setup.tcl and common_setup.tcl.
  - Creating initial ILM, FRAM for each block (before detailed block implementation) and linking to the top-level.
    This allows an early timing check of the top level CEL. Note: You should always finish block implementation to get accurate ILM and FRAM.

- Now you will see sub-directories for all your blocks and top-level design.
  Proceed to each block for detailed implementation.

* See the application note for more details on the flow and data structure


STEP 2. Block implementation: Run Makefile from each of the block directories: make ic &
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- This runs IC Compiler RM for block implementation.  At the end, it generates ILM and FRAM for the block.

* When all blocks are completed, you can move on to top-level integration.


STEP 3. Top-level integration: Run Makefile from top directory: make ic &
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- This runs IC Compiler RM for top-level integration.
- It is already set up to reference to the block libraries to use ILM and FRAM (initial or after detailed block implementation).
  Typically, this step is run after STEP 2 is completed.  However, you can run this step after STEP 1 to perform some early checks.