📄 outputs_icc.tcl
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## ICC RM Version: B-2008.09 ###########################################Outputs Script#######################################source -echo icc_setup.tcl##Open Designopen_mw_lib $MW_DESIGN_LIBRARYif {![file exists [which $PT_DIR/pt_shell]] } { open_mw_cel $ICC_CHIP_FINISH_CEL} else { open_mw_cel $ICC_SIGNOFF_OPT_CEL}link##Change Nameschange_names -rules verilog -hierarchysave_mw_cel -as change_names_iccclose_mw_celopen_mw_cel change_names_icclink##Verilogset_app_var verilogout_no_tri truewrite_verilog $RESULTS_DIR/$DESIGN_NAME.output.vwrite_verilog -pg_ports -output_net_name_for_pg $RESULTS_DIR/$DESIGN_NAME.output.pg.v##SDCset_app_var write_sdc_output_lumped_net_capacitance falseset_app_var write_sdc_output_net_resistance falseif {!$MCMM_MODE } { write_sdc $RESULTS_DIR/$DESIGN_NAME.output.sdc } else { set_active_scenarios [lminus [all_scenarios] $ICC_MCMM_CTS_SCENARIO] foreach scenario [all_active_scenarios] { set_active_scenario $scenario current_scenario $scenario write_sdc $RESULTS_DIR/$DESIGN_NAME.$scenario.output.sdc }; }##Parasiticsextract_rc -coupling_cap#write_parasitics -format SPEF -output $RESULTS_DIR/$DESIGN_NAME.output.spefwrite_parasitics -format SBPF -output $RESULTS_DIR/$DESIGN_NAME.output.sbpf##DEFwrite_def -output $RESULTS_DIR/$DESIGN_NAME.output.def###GDSII##Set options - usually also include a mapping file (-map_layer)# set_write_stream_options \# -child_depth 99 \# -output_filling fill \# -output_outdated_fill \# -output_pin geometry \# -keep_data_type# write_stream -lib_name $MW_DESIGN_LIBRARY -format gds $RESULTS_DIR/$DESIGN_NAME.gdsif {$ICC_CREATE_MODEL } { save_mw_cel -as $DESIGN_NAME close_mw_cel open_mw_cel $DESIGN_NAME create_ilm -include_xtalk ##create FRAM create_macro_fram ##create Antenna Info if {$ICC_FIX_ANTENNA } { extract_zrt_hier_antenna_property -cell_name $DESIGN_NAME } close_mw_cel }exit
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