feasibility_on_plangroups_dp.tcl

synopsys icc 使用参考脚本

##################################################################################################
# ICC Hierarchical RM								 	 	 #
# feasibility_on_plangroups_dp: PNS/PNA, IPO, and PGAR					 	 #
# Version B-2008.09   							 	 	 	 #
##################################################################################################


source icc_setup.tcl
gui_set_current_task -name {Design Planning}

open_mw_lib $MW_DESIGN_LIBRARY
copy_mw_cel -from $ICC_DP_CREATE_PLANGROUPS_CEL -to $ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL
open_mw_cel $ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL
link



source ./icc_scripts/common_placement_settings_icc.tcl



##############################################################################################################################
## Power Network Synthesis (PNS)
##############################################################################################################################

## If you want to use your existing virtual pad file, please load it before PNS by the following:
## (virtual pad is created by user or tool to serve as temporary source of power or ground for power network synthesis consideration)
#       create_fp_virtual_pad -load_file $YOUR_PNS_VIRTUAL_PAD_FILE

##############################################################################################################################
## Setup fp_synthesize_rail based on your design style
############################################################################################################################## 
## If you're running on a block with existing PG pins, please add following option
#	-use_pins_as_pads
#
## If you're running o/ a block without existing PG pins, please add following option
#       -use_strap_ends_as_pads
#
## If you're running on top level with existing power pads, please add  one of the following options
#	-pad_masters $PNS_PAD_MASTERS                   (specify pad cell masters) or
#	-read_pad_master_file $PNS_PAD_MASTER_FILE      (specify a file with pad cell masters) or
#	-read_pad_instance_file $PNS_PAD_INSTANCE_FILE  (specify a file with pad cell instances)
#
## If you're running on top level without existing power pads, please add following option
## Note: This feature is not available until 2007.03  
#       -synthesize_power_pads
#
## If you'd like to simulate standard cell rail during PNS, please add the following option
#       -create_virtual_rails $PNS_VIRTUAL_RAIL_LAYER
synthesize_fp_rail -power_budget $PNS_POWER_BUDGET -voltage_supply $PNS_VOLTAGE_SUPPLY -output_directory $PNS_OUTPUT_DIR -nets $PNS_POWER_NETS -synthesize_power_plan

commit_fp_rail



##############################################################################################################################
## Power Network Synthesis (PNA)
##############################################################################################################################

## Setup fp_analyze_rail based on your design style
## If you're running on a block with existing PG pins, please add following option
#       -use_pins_as_pads
#
## If you're running on a block without existing PG pins, please add following commands before fp_analyze_rail
#       create_fp_virtual_pad -load_file pna_output/strap_end.VDD.vpad (VDD is your power net name)
#       create_fp_virtual_pad -load_file pna_output/strap_end.VSS.vpad (VSS is your ground net name
##   then add the following option to fp_analyze_rail
#       -use_pins_as_pads
#
## If you're running on top level with existing power pads, please add one of the following options
#       -pad_masters $PNS_PAD_MASTERS                   (specify pad cell masters) or
#       -read_pad_master_file $PNS_PAD_MASTER_FILE      (specify a file with pad cell masters) or
#       -read_pad_instance_file $PNS_PAD_INSTANCE_FILE  (specify a file with pad cell instances)
#
## If you're running on top level without existing power pads, please add following commands before fp_analyze_rail
#       create_fp_virtual_pad -load_file pna_output/strap_end.VDD.vpad (VDD is your power net name)
#       create_fp_virtual_pad -load_file pna_output/strap_end.VSS.vpad (VSS is your ground net name
#
## If you'd like to simulate standard cell rail during PNS, please add the following option
#       -create_virtual_rails $PNS_VIRTUAL_RAIL_LAYER
analyze_fp_rail -power_budget $PNS_POWER_BUDGET -voltage_supply $PNS_VOLTAGE_SUPPLY -output_directory $PNS_OUTPUT_DIR -nets $PNS_POWER_NETS



#########################################################################################
## Check Placement QoR									#
#########################################################################################
set_fp_flow_strategy -plan_group_aware_routing true
route_fp_proto -effort medium -congestion_map_only
save_mw_cel -as ${ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL}_groute_after_pna

extract_rc
create_qor_snapshot -name ${ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL}_groute_after_pna -qor -timing -constraint



#########################################################################################
## Optimization										#
#########################################################################################
source ./icc_scripts/common_optimization_settings_icc.tcl
set_dont_touch_placement [all_macro_cells]
set compile_instance_name_prefix dp_ipo

## AHFS Options for optimize_fp_timing
#	set_ahfs_options -remove_effort none -hf_threshold 20

optimize_fp_timing
## Here're some options to consider:
#	-fix_design_rule (fix max tran violations)
#	-effort effort (medium and high)	
#  	-report_qor (report QoR of optimization)

create_qor_snapshot -name ${ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL}_ipo -qor -timing -constraint
save_mw_cel
report_timing -cap -tran -input -net -delay max -attribute -physical > ${REPORTS_DIR}/${ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL}_ipo.rpt



exit