pin_assignment_budgeting_dp.tcl

synopsys icc 使用参考脚本

##################################################################################################
# ICC Hierarchical RM								 	 	 #
# optimization_dp: Clokc Tree Planning, Pin Assignment, IPO on Feedthrough, and Timing Budgetting#
# Version B-2008.09										 #
##################################################################################################


source icc_setup.tcl
gui_set_current_task -name {Design Planning}

open_mw_lib $MW_DESIGN_LIBRARY
copy_mw_cel -from $ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL -to $ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL
open_mw_cel $ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL
link



source ./icc_scripts/common_placement_settings_icc.tcl



#########################################################################################
## Clock Tree Planning (Optional; uncomment the section to use it)			#
#########################################################################################
#if {$ICC_DP_CTP} {
#	if {$ICC_DP_CTP_ANCHOR_CEL != ""} {
#		set_fp_clock_plan_options -anchor_cell $ICC_DP_CTP_ANCHOR_CEL -output_directory ${RESULTS_DIR}/ctp_output -route_mode global
#	}
#	## Here're some options for set_fp_clock_plan_options to consider:
#	#	-clock_nets {CLK}
#	#	-no_feeds_plan_group [get_plan_groups *]
#	#	-keep_block_tree false
#	
#	report_fp_clock_plan_options
#	
#	compile_fp_clock_plan
#	
#	save_mw_cel -as ${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_ctp
#}



#########################################################################################
## Pin Assignment									#
#########################################################################################
if {!$ICC_DP_CTP} {mark_clock_tree -clock_net}


if {$ICC_DP_ALLOW_FEEDTHROUGH} {

set_fp_pin_constraints -allow_feedthroughs on -exclude_clock_feedthroughs on
## Here're some other options to consider:
#	-keep_buses_together on|off

}

report_fp_pin_constraints

set_fp_flow_strategy -plan_group_aware_routing true
route_global

analyze_fp_routing -finalize plan_groups
save_mw_cel -as ${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_pincut

# analyze_fp_routing -list_feedthrough $file
# use the following to view feedthough nets:
# File/Task/Design Planning/Pin Assignment/Analyze Pin Routing




if {$ICC_DP_ALLOW_FEEDTHROUGH} {

#########################################################################################
## Optimization on Feedthrough Nets							#
#########################################################################################
set compile_instance_name_prefix dp_ipo_ft
optimize_fp_timing -feedthrough_buffering_only
save_mw_cel -as ${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_ipo_ft

report_timing -cap -tran -input -net -delay max -attribute -physical > ${REPORTS_DIR}/${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_ipo_ft.rpt
create_qor_snapshot -name ${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_ipo_ft -qor -timing -constraint

}




#########################################################################################
## Timing Budgeting									#
#########################################################################################
check_fp_timing_environment -unbudgetable_pins -unconstrained_pins > $REPORTS_DIR/${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_check_timing_env.rpt

## If clock tree planning is performed on the design, set the following to let timing budgeting recognize the clock tree:
#	set synthesized_clocks TRUE
#	set_propagated_clock [get_clocks *]

allocate_fp_budgets -file_format_spec {./sdc/m.sdc}
# use ./sdc/m.sdc to write budgets to "sdc" dir in files named based on cell master
# use ./sdc/i.sdc to write budgets to "sdc" dir in files named based on instance name
# We're using cell master style through out the RM

check_fp_budget_result -block $ICC_DP_PLAN_GROUPS -file_name ${REPORTS_DIR}/${ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL}_budget_result.rpt

# remove_propagated_clock [get_clocks *]



save_mw_cel
close_mw_lib

exit