readme.icc-rm.txt

synopsys icc 使用参考脚本

IC Compiler Reference Methodology
==================================

Features
========
- Provides self-documenting reference methodology scripts for place and route using IC Compiler.
- Provides the basic flow from netlist to GDS out
- Includes IC Compiler Design Planning Reference Methodology (ICC-DP-RM), which allows you to explore different floorplans
- Includes parallel flows for multivoltage (MV) and multicorner-multimode (MCMM)
- Starting in version A-2007.12-SP1, also includes the Hierarchical Reference Methodology (ICC-HRM)
- Includes signoff_opt (optimization using Synopsys' sign-off extraction and timing analysis tool)
- Includes DFT Compiler and Power Compiler reference methodologies
- Designed to work with the Design Compiler Reference Methodology as the first step

Description
===========
The IC Compiler Reference Methodology (ICC-RM) provides you with a set of reference scripts that serve as a recommended guideline for developing IC Compiler scripts. 
The scripts can be run out of the box, enabling you to get a fully optimized and routed design right away. In addition to the basic flow, which includes IC Compiler Design Planning-RM and sign-off-driven optimization, there are parallel flows that can be run: 

- Design-for-test scan chain reordering flow 
- Leakage and dynamic power optimization flow 
- Multivoltage (MV) flow (including MTCMOS): for both non-UPF and UPF-based flows 
- Multicorner-multimode (MCMM) flow 
- All key chip-finishing flow steps 
- Physical hierarchical flow 
- Zroute flow 

Contents
========
The ICC-RM includes the following scripts: 

2 setup scripts 

common_setup.tcl: 
- Includes common design setup variables for Design Compiler and IC Compiler Reference Methodologies 
icc_setup.tcl: 
- Specified additional variables used by ICC-RM only 

10 constraint and optimization scripts 

icc_scripts/init_design_icc.tcl:  
- Reads the logical netlist and constraints, creates the floorplan (or reads the floorplan via DEF), and generates a zero interconnect timing report. 

icc_scripts/place_opt_icc.tcl:  
- Runs placement and placement-based optimization. 

icc_scripts/clock_opt_cts_icc.tcl:  
- Runs clock tree synthesis (CTS) and optimization.

icc_scripts/clock_opt_psyn_icc.tcl: 
- Runs post-CTS optimization.

icc_scripts/clock_opt_route_icc.tcl: 
Routes the clocks with the specified nondefault routing rules. 

icc_scripts/route_icc.tcl: 
- Runs routing. Crosstalk delta delay is enabled by default. 

icc_scripts/route_opt_icc.tcl: 
- Runs postroute optimization. Crosstalk delta delay is enabled by default. 

icc_scripts/chipfinish_icc.tcl: 
- Runs several chipfinishing steps, such as timing-driven metal fill, detail route wire spreading to reduce the critical area, antenna fixing. 

icc_scripts/signoff_opt_icc.tcl: 
- Runs sign-off-driven optimization, using of Star-RCXT and PrimeTime to create a design that is ready for sign-off. 

icc_scripts/outputs_icc.tcl: 
- Creates several output files: Verilog, DEF, SPEF, GDS, others. 


The floorplanning scripts (flat and hierarchical) are in the icc_dp_scripts directory. 
The Zroute scripts are in the icc_zrt_scripts directory. 


To run
======
To run the classic router RM, execute the same command as before :
 make (-f Makefile) ic

To run the Zroute RM, use the new makefile as follows :
 make -f Makefile_zrt ic