release_notes.icc-hrm.txt

synopsys icc 使用参考脚本

IC Compiler Hierarchical Reference Methodology (RM) Release Notes

Differences in IC Compiler Hierarchical RM B-2008.09 versus IC Compiler Hierarchical RM A-2007.12-SP5:
o In icc_dp_scripts/create_plangroups_dp.tcl
  * macros_on_edge default in the tool is changed to auto so flow is updated
    set_fp_placement_strategy -macro_on_edge off
    create_fp_placement
    shape_fp_blocks
    set_fp_placement_strategy -macro_on_edge auto
    create_fp_placement
  * create_fp_plan_group_padding syntax is changed in the tool so script is updated
    create_fp_plan_group_padding -internal_widths {2 2 2 2} -external_widths {2 2 2 2} [get_plan_groups *]
o In icc_dp_scripts/pin_assignment_budgeting_dp.tcl
  * ICC_DP_ALLOW_FEEDTHRU variable is renamed to ICC_DP_ALLOW_FEEDTHROUGH
  * analyze_fp_routing syntax is changed in the tool so script is updated
    analyze_fp_routing -finalize plan_groups
o In icc_setup.tcl
  * Variable ICC_DP_SPLIT_TOP_CEL_NAME is replaced by ICC_DP_COMMIT_CEL


Differences in IC Compiler Hierarchical RM A-2007.12-SP5 versus IC Compiler Hierarchical RM A-2007.12-SP4:
o In Makefile_hier:
  * The single step hierarchy_dp is now split into 4 steps, with each corresponding to a script. This should make it easier to stop, check, and modify your design.
  * The 4 steps are grouped based on functionalities: create_plangroups_dp, feasibility_on_plangroups_dp, pin_assignment_budgeting_dp, and commit_dp.
o In icc_setup.tcl, you can set starting CEL name of the steps from the following variables:
  * set ICC_DP_CREATE_PLANGROUPS_CEL "create_plangroups_dp"
  * set ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL "feasibility_on_plangroups_dp"
  * set ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL "pin_assignment_budgeting_dp"
  * set ICC_DP_COMMIT_CEL "commit_dp"
o In icc_dp_scripts: a new file is created for each of the new steps:
  * create_plangroups_dp.tcl: plangroup creation, shaping and placement
  * feasibility_on_plangroups_dp.tcl: PNS/PNA, proto route, and in place optimization
  * pin_assignment_budgeting_dp.tcl: pin assignment and timing budgeting
  * commit_dp.tcl: commit and split design


Differences in IC Compiler Hierarchical RM A-2007.12-SP4 versus IC Compiler Hierarchical RM A-2007.12-SP2:
o In icc_dp_scripts/hierarchy_dp.tcl:
  * "Create Plangroups" section hard-coded -utilization 0.7 option for create_plan_groups command has been removed; 
    the plangroup utilization will now be determined by the tool.
  * Comments of "Create Plangroups" section has been updated to list all possible entry points.
  * "Create Plangroups" section now checks for $ICC_DP_PLANGROUP_FILE first instead of $ICC_DP_PLANGROUPS; 
    this is useful if you have run through it the first time and would like to simply reuse the dumped out plangroup file.
  * "Plangroup Shaping" section is updated. If you provide $ICC_DP_PLANGROUP_FILE, 
     plangroup shaping will be skipped but virtual flat placement on plangroups can still run.
  * "Clock Tree Planning" section is updated $ICC_DP_CTP is added as new control. 
    If you want to use clock tree planning, uncomment the whole section and then you can use the variable to control it. 
    Note that you may still have to set additional options for clock tree planning to work properly.
  * "Pin Assignment" section is updated with remove_route_by_type command removed.
o In icc_dp_scripts/prepare_block_dp.tcl:
  * read_sdc command for block preparation is now removed as SDC constraints are now pushed down to the block automatically by the tool.


Differences in IC Compiler Hierarchical RM A-2007.12-SP2 versus IC Compiler Hierarchical RM A-2007.12-SP1:
o The descriptions for ICC_DP_PLAN_GROUPS and ICC_DP_CTP_ANCHOR_CEL in icc_setup.tcl have been updated.
o icc_dp_scripts/hierarchy_dp.tcl has been updated:
  * Clock tree planning section, in the comments, 
  * checking for ICC_DP_CTP_ANCHOR_CEL added before set_fp_clock_plan_options.
o icc_dp_scripts/prepare_block_dp.tcl has been updated:
  * Now PNS_BLOCK_MODE will be set to true in icc_setup.tcl for sub-blocks.