icc_setup.tcl

synopsys icc 使用参考脚本

######################################################################################################################
#####################   ICC DESIGN PLANNING SPECIFIC (variables for ICC DP-RM and ICC Hierarchical-RM)  ##############
######################################################################################################################

###################################################
## Hierarchical Partitioning variables
###################################################

set MW_ILM_LIBS                         ""              ;# add ILMs for block level FRAMs not used by DCT
set ICC_DP_PLAN_GROUPS                  ""		;# full module names from which plan groups will be created
                                                        ;#   space deliminated list: top/A top/B top/C
set ICC_DP_PLANGROUP_FILE               ""              ;# floorplan file contains plan group creation and location which should be the output of write_floorplan
set ICC_DP_CTP				false		;# set it to true to enable clock tree planning; please uncomment the section in hierarchical_dp.tcl first
set ICC_DP_CTP_ANCHOR_CEL               ""              ;# anchor cell for clock tree planning (anchor cell is required if you uncomment clock tree planning in scripts);
							;#   cell master of one mid-sized buffer
set ICC_DP_SPLIT_TOP_CEL_NAME           "hierarchy_dp"  ;# top CEL name used with split_mw_lib; default is hierarchy_dp (no need to change it)



###################################################
## Design Planning Virtual Flat Placement variables
###################################################

set ICC_DP_FIX_MACRO_LIST		  ""		;# ""|skip|"a_list_of_macros"; fix all macos OR skip fix OR fix specified macros before placement
set CUSTOM_ICC_DP_PLACE_CONSTRAINT_SCRIPT ""            ;# Put your set_keepout_margin and fp_set_macro_placement_constraint in this file 
set ICC_DP_EXPLORE_MODE			true		;# true|false; turn on explore mode
set ICC_DP_EXPLORE_STYLE		"default"	;# valid options are: default | placement_only | no_pns_pna | no_ipo
							;# default: place -> pns/pna -> ipo -> final groute,snapshot,QOR,timing,and outputs 
							;# placement_only: skips pns/pna and ipo from default | no_pns_pna: skips pna/pns from default 
                                                        ;# | no_ipo: skips ipo from default 
set ICC_DP_EXPLORE_SAVE_CEL_EACH_STEP 	false		;# true|false; save 3 additional CEL after placement, ipo, and pns in explore mode (requires more disk space)
set ICC_DP_EXPLORE_REPORTING_EACH_STEP	false		;# true|false; generate QoR snapshot and timing report after each step (longer run time)
set ICC_DP_EXPLORE_USE_GLOBAL_ROUTE 	false		;# true|false; use route_global OR fp_proto_route (default)
set ICC_DP_EXPLORE_SAVE_CEL_AFTER_GROUTE true		;# true|false; save 2 additional CEL after global route: one after placement and one at the end
set ICC_DP_VERBOSE_REPORTING		false		;# true|false; generate additional reports before placement
set ICC_DP_PLACEMENT_VA_NET_WEIGHT 	2		;# valid values are from 0 to 9; applied when MV_MODE is true and used by set_fp_placement_strategy -voltage_area_interface_net_weight
set ICC_DP_SET_HFNS_AS_IDEAL_THRESHOLD	""		;# integer; specify a threshold to set nets with fanout larger than it as ideal nets
set ICC_DP_SET_MIXED_AS_IDEAL		true		;# true|false; set mixed clock/signal paths as ideal nets


####################################################
## Design Planning Power Network Synthesis variables
####################################################

set CUSTOM_ICC_DP_PNS_CONSTRAINT_SCRIPT ""              ;# File to add PNS constraints which is loaded before running PNS
set PNS_POWER_NETS         		"${MW_POWER_NET} ${MW_GROUND_NET}" ;# Target nets for PNS; syntax is "your_power_net your_ground_net" 
set PNS_POWER_BUDGET       		"1000"          ;# Unit in milliWatts; default is 1000
set PNS_VOLTAGE_SUPPLY     		"1.5"           ;# Unit in Volts; default is 1.5
set PNS_TARGET_VOLTAGE_DROP     	"250"	        ;# Unit in milliVolts. Tool default is 10% of PNS_POWER_BUDGET
set PNS_BLOCK_MODE         		false         ;# true|false; specify if the design is block or top level; It turns on correspondant options in PNS and PNA
set PNS_PAD_MASTERS        		""		;# Only for top level design. Specify cell masters for power pads, e.g. "pv0i.FRAM pv0a.FRAM"
set PNS_PAD_INSTANCE_FILE  		""              ;# Only for top level design. Specify the file with a list of power pad instances
set PNS_PAD_MASTER_FILE    		""		;# Only for top level design. Specify the file with a list of power pad masters
## Please provide only one of PNS_PAD_MASTERS, OR PNS_PAD_INSTANCE_FILE, OR PNS_PAD_MASTER_FILE 
set PNS_VIRTUAL_RAIL_LAYER 		""              ;# Specify the metal layer you want to use as virtual rail
set PNS_OUTPUT_DIR         		"./pna_output"  ;# Output directory for PNS and PNA output files



##########################################################################################
#####################      NO NEED TO CHANGE IF DCT IS USED BEFORE          ##############
##########################################################################################

set ICC_IN_VERILOG_NETLIST_FILE "$DESIGN_NAME.mapped.v" ;#1 to n verilog input files, spaced by blanks
set ICC_IN_SDC_FILE             "$DESIGN_NAME.mapped.sdc"
set ICC_IN_DDC_FILE             "$DESIGN_NAME.mapped.ddc"
set ICC_IN_UPF_FILE             "$DESIGN_NAME.mapped.upf"
set ICC_IN_SCAN_DEF_FILE        "$DESIGN_NAME.mapped.scandef"
set MW_DESIGN_LIBRARY           "${DESIGN_NAME}_LIB"    ;# milkyway design library

##########################################################################################
#########################     USAGE OF ABOVE VARIABLES      ##############################
#########################   DO NOT CHANGE BELOW THIS LINE   ##############################
##########################################################################################

set ICC_IN_SAIF_FILE            "$DESIGN_NAME.saif"     ;# SAIF file for dynamic power opto
set ICC_SAIF_INSTANCE_NAME      $DESIGN_NAME            ;# the instance in the SAIF file containing the switching activity

set REPORTS_DIR                 "reports"               ;# Directory to write reports.
set RESULTS_DIR                 "results"               ;# Directory to write output data files 

## Logical libraries
set_app_var search_path                 ". ./icc_scripts ./icc_zrt_scripts ./icc_dp_scripts $ADDITIONAL_SEARCH_PATH $search_path"
set_app_var target_library              " $TARGET_LIBRARY_FILES"
set_app_var link_library                "* $TARGET_LIBRARY_FILES $ADDITIONAL_LINK_LIB_FILES"


if { ! [file exists $RESULTS_DIR] } {
  file mkdir $RESULTS_DIR
}
if { ! [file exists $REPORTS_DIR] } {
  file mkdir $REPORTS_DIR
}


## Min Max Library Relationships
if {$MIN_LIBRARY_FILES != "" } {
  foreach {max_library min_library} $MIN_LIBRARY_FILES {
    set_min_library $max_library -min_version $min_library
  }
}


## Power/Ground Net Naming
set mw_logic1_net               $MW_POWER_NET
set mw_logic0_net               $MW_GROUND_NET


## Reference Libraries
if { ![file exists [which $MW_REFERENCE_CONTROL_FILE]]} {
 if {[file exists $MW_DESIGN_LIBRARY/lib]} {
   set_mw_lib_reference $MW_DESIGN_LIBRARY -mw_reference_library "$MW_REFERENCE_LIB_DIRS $MW_ILM_LIBS"
 }
}


## PD4 is not always used
if {![info exists PD4]} {set PD4 ""}

## Check UPF mode

##START_EVAL
if {$MV_MODE == "UPF"} {
##START_TOOL_SPC
  if { ![shell_is_in_upf_mode]} {
  echo "SCRIPT-Error: MV_MODE is UPF, but shell is not in UPF mode, please start ICC with -upf_mode"
 }
##END_TOOL_SPC
}
##END_EVAL


## Avoiding too many messages
set_message_info -id PSYN-040 -limit 10 ;# Dont_touch for fixed cells
set_message_info -id PSYN-087 -limit 10 ;# Port inherits its location from pad pin
set_message_info -id LINT-8   -limit 10 ;# input port is unloaded

set_app_var check_error_list "$check_error_list LINK-5"