icc_setup.tcl

synopsys icc 使用参考脚本

##########################################################################################
# Variables for ICC-RM, ICC DP-RM, and ICC Hierarchical-RM
# Script: icc_setup.tcl
# Version: B-2008.09
# Copyright (C) 2007, 2008 Synopsys All rights reserved.
##########################################################################################

##########################################################################################

# sourcing the common variables
source -echo common_setup.tcl


###############################
## General ICC variables
###############################

set ICC_INPUT_CEL               "${DESIGN_NAME}_DCT"   ;# CEL created in DCT

set PNET_METAL_LIST               ""                   ;# List of metals in the design to be used for (partial) pnet options
set PNET_METAL_LIST_COMPLETE	  ""		       ;# List of metals in the design to be used for (complete) pnet options
set ICC_IN_DONT_USE_FILE          ""                   ;# file of master don't use commands 
set ICC_FIX_HOLD_PREFER_CELLS     ""                   ;# Syntax: library/cell_name - Example: slow/DLY1X1 slow/DLY1X4
set AREA_CRITICAL_RANGE_PRE_CTS   ""                   ;# area critical range use during area opto during place_opt
set AREA_CRITICAL_RANGE_POST_CTS  ""                   ;# area critical range use during area opto during post CTS opt
set AREA_CRITICAL_RANGE_POST_RT   ""                   ;# area critical range use during area opto during route_opt
set POWER_CRITICAL_RANGE_PRE_CTS  ""                   ;# power critical range use during area opto during place_opt
set POWER_CRITICAL_RANGE_POST_CTS ""                   ;# power critical range use during area opto during post CTS opt
set POWER_CRITICAL_RANGE_POST_RT  ""                   ;# power critical range use during area opto during route_opt
set ICC_NUM_CPUS                  1                    ;# used during placement & distributed routing
set ICC_NUM_THREADS               1                    ;# number of threads for Zroute 
 
##START_RM_VARIABLES
set ICC_STRATEGY                  "QOR"                ;# TTR|QOR
set LEAKAGE_POWER                 FALSE                ;# set to TRUE when enabling leakage Flow
set DYNAMIC_POWER                 FALSE                ;# set to TRUE when enabling dynamic power Flow
set DFT                           FALSE                ;# set to TRUE when enabling scan reordering Flow
set ICC_CREATE_MODEL              FALSE                ;# used for ILM/FRAM creation for the blocks in HRM
set MV_MODE                       "NONE"               ;# NONUPF|UPF|NONE
set AO_MODE                       FALSE                ;# enable the Always On synthesis mode
set MCMM_MODE                     FALSE                ;# set to TRUE when enabling MCMM Flow
set ICC_DBL_VIA                   TRUE                 ;# TRUE|FALSE ; will start the detail route wire spreading
set ICC_FIX_ANTENNA               FALSE                ;# TRUE|FALSE : will start antenna fixing
set ADD_FILLER_CELL               FALSE                ;# TRUE|FALSE ; will start the std cells filler insertion
set ICC_REDUCE_CRITICAL_AREA      TRUE                 ;# TRUE|FALSE ; will start the detail route wire spreading
set ADD_METAL_FILL                TRUE                 ;# TRUE|FALSE ; will start timing driven metal fill
set ICC_INIT_DESIGN_INPUT         "MW"                 ;# VERILOG|DDC|MW - starting point
set ICC_FLOORPLAN_INPUT           "DEF"                ;# DEF|FP_FILE|CREATE|USER_FILE|SKIP
set CUSTOM_CONNECT_PG_NETS_SCRIPT ""                   ;# If not defined as "", source this file
set ICC_DP_ALLOW_FEEDTHROUGH	  FALSE		       ;# TRUE|FALSE ; ICC Hierarchical RM only ; allow feedthrough creation during pin assignment 
##END_RM_VARIABLES



###############################
## Floorplan Input variables          		    
###############################
set ICC_IN_DEF_FILE		  ""		;# Complete floorplan file in DEF format
set ICC_IN_FLOORPLAN_FILE	  ""		;# Complete floorplan file generated by write_floorplan 
set ICC_IN_FLOORPLAN_USER_FILE	  ""		;# Complete floorplan file generated by user ;this file will simply be sourced
set ICC_IN_TDF_FILE 		  ""		;# TDF file which contains pad or pin information
set ICC_IN_PHYSICAL_ONLY_CELLS_CREATION_FILE "" ;# a file to include physical only cell creation commands to be sourced
                                                ;# e.g. create_cell {vdd1left vdd1right vdd1top vdd1bottom} pvdi
set ICC_IN_PHYSICAL_ONLY_CELLS_CONNECTION_FILE "" ;# a file to include physical only cell connection commands to be sourced
                                                  ;# e.g. derive_pg_connection -power_net $MW_POWER_NET -power_pin $MW_POWER_PORT -ground_net $MW_GROUND_NET -ground_pin $MW_GROUND_PORT -cells {vdd1left vdd1right vdd1top vdd1bottom}



###############################
## MV Input variables                       
###############################
set AO_INSTANCES                        {}     ;# list of instances that require AO synthesis ( e.g. {TOP/INST2, TOP/INST3}
set ICC_DP_AUTO_CREATE_VA               false  ;# automatically create voltage area based on user specified utilization
set CUSTOM_POWER_SWITCH_SCRIPT          ""     ;# define in here the headers_footers and connect the sleep pin
set LS_CELLS                            ""     ;# e.g. "LVL" if each Level Shifter contains LVL in its name
set RR_CELLS                            ""     ;# e.g. "RSD" if each Retention Register contains RSD in its name
set AO_CELLS                            ""     ;# name string for the Always On cells
set CUSTOM_SECONDARY_POWER_ROUTE_SCRIPT ""     ;# define in here the pre_route_standard_cells command for the AO/RR cells.

###############################
## MCMM Input variables                             
###############################

set ICC_MCMM_CTS_SCENARIO         ""    ;# the scenarios to be used during CTS  - ensure all clocks are defined here
set ICC_MCMM_SCENARIOS_FILE       ""    ;# file containing all scenario definitions - example in icc_scripts/mcmm.scenarios.example



###############################
## SIGNOFF_OPT Input variables
###############################
set PT_DIR ""                          ;# path to PT bin directory
set PT_SDC_FILE ""                     ;# optional file in case PT has different SDC that what is available in the ICC database
set STARRCXT_DIR ""                    ;# path to Star-rcxt bin directory
set STARRCXT_MAX_NXTGRD ""             ;# MAX NXTGRD file
set STARRCXT_MIN_NXTGRD ""             ;# MIN NXTGRD file
set STARRCXT_MAP_FILE "$MAP_FILE"      ;# NXTGRD mapping file, defaults to TLUPlus mapping file, but could be different


###############################
## Clock Tree variables
###############################

set ICC_CTS_LAYER_LIST            ""            ;# clock tree layers, usually M3 and above
                                                ;# e.g. set ICC_CTS_LAYER_LIST "M3 M4 M5"
set ICC_CTS_REF_LIST              ""            ;# cells ;# used for CTS 
                                                ;#   space deliminated list: cell1 cell2 
set ICC_CTS_REF_DEL_INS_ONLY      ""            ;# cells for CTS delay insertion :
                                                ;#   space deliminated list: cell1 cell2
set ICC_CTS_REF_SIZING_ONLY       ""            ;# cells for CTS that are for sizing only 
                                                ;#   space deliminated list: cell1 cell2

###############################
## Chipfinishing variables
###############################

## antenna fixing
set ANTENNA_RULES_FILE           ""             ;# defines the antenna rules

## critical area reduction 
set TIMING_PRESERVE_SLACK        "0.1"        ;# amount is passed as setup.hold slack threshold for wire_spreading/widening


set FILLER_CELL_METAL            ""             ;# space separated list of filler cells 
set FILLER_CELL                  ""             ;# ADD_FILLER_CELL - space separated 


###############################
## Cellname variables
###############################

set ICC_FLOORPLAN_CEL            "init_design_icc"
set ICC_PLACE_OPT_CEL            "place_opt_icc"
set ICC_CLOCK_OPT_CTS_CEL        "clock_opt_cts_icc"
set ICC_CLOCK_OPT_PSYN_CEL       "clock_opt_psyn_icc"
set ICC_CLOCK_OPT_ROUTE_CEL      "clock_opt_route_icc"
set ICC_ROUTE_CEL                "route_icc"
set ICC_ROUTE_OPT_CEL            "route_opt_icc"
set ICC_CHIP_FINISH_CEL          "chip_finish_icc"
set ICC_SIGNOFF_CEL              "signoff_icc"
set ICC_SIGNOFF_OPT_CEL          "signoff_opt_icc"
set ICC_DP_CREATE_PLANGROUPS_CEL "create_plangroups_dp"
set ICC_DP_FEASIBILITY_ON_PLANGROUPS_CEL "feasibility_on_plangroups_dp"
set ICC_DP_PIN_ASSIGNMENT_BUDGETING_CEL	 "pin_assignment_budgeting_dp"
set ICC_DP_COMMIT_CEL		 "commit_dp"