dc_top.tcl

synopsys dc_shell 用户手册

source -echo -verbose dc_setup.tcl

#################################################################################
# Design Compiler Top-Level Reference Methodology Script for Hierarchical Flow
# Script: dc_top.tcl
# Version: B-2008.09 (Oct. 3, 2008)
# Copyright (C) 2007, 2008 Synopsys All rights reserved.
#################################################################################

#################################################################################
# Additional Variables
#
# Add any additional variables needed for your flow here.
#################################################################################

# No additional flow variables are being recommended

#################################################################################
# Setup for Formality verification
#
# SVF should always be written to allow Formality verification
# for advanced optimizations.
#################################################################################

set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf


#################################################################################
# Setup SAIF Name Mapping Database
#
# Include an RTL SAIF for better power optimization and analysis.
#
# saif_map should be issued prior to RTL elaboration to create a name mapping
# database for better annotation.
################################################################################

# saif_map -start

#################################################################################
# Read in the RTL Design
#
# Read in the RTL source files or read in the elaborated design (DDC).
# Use the -format option to specify: verilog, sverilog, or vhdl as needed.
#################################################################################

define_design_lib WORK -path ./WORK

# Do not include the RTL for the hierarchical designs
# when reading in the top-level design.
analyze -format verilog ${RTL_SOURCE_FILES}
elaborate ${DESIGN_NAME}

# Remove the RTL version of the hierarchical blocks in case they were read in

if { ${DDC_HIER_DESIGNS} != ""} {
  remove_design -hierarchy ${DDC_HIER_DESIGNS}
}

if { ${DC_ILM_HIER_DESIGNS} != ""} {
  remove_design -hierarchy ${DC_ILM_HIER_DESIGNS}
}

if { ${ICC_ILM_HIER_DESIGNS} != ""} {
  remove_design -hierarchy ${ICC_ILM_HIER_DESIGNS}
}


# Store the elaborated design without the hierarchical physical blocks
write -hierarchy -format ddc -output ${RESULTS_DIR}/${DESIGN_NAME}.elab.ddc

# OR

# You can read an elaborated design from the same release.
# Using an elaborated design from an older release will not give the best results.

# Important: Make sure that the elaborated DDC does not contain the physical subdesigns (removed above).

# read_ddc ${DESIGN_NAME}.elab.ddc

# DO NOT LINK yet or Presto will rebuild the RTL version of the physical blocks.
# Finish loading the physical blocks below before linking.

#################################################################################
# Load Hierarchical Designs
#################################################################################

# Read in compiled hierarchical blocks
# For topographical mode top-level synthesis all physical blocks are required to
# be compiled in topographical mode.

foreach design ${DDC_HIER_DESIGNS} {
  read_ddc ${design}.mapped.ddc
}

foreach design ${DC_ILM_HIER_DESIGNS} {
  read_ddc ${design}.mapped.ILM.ddc
}

current_design ${DESIGN_NAME}
link

# Check to make sure that all the correct designs were linked
# Pay special attention to the source location of your physical blocks
list_designs -show_file

# Read in CTL test models for ICC-ILM blocks to ensure DFT info is present
foreach design ${ICC_ILM_HIER_DESIGNS} {
  read_test_model -format ctl -design ${design} ${design}.mapped.ctl
}

# Don't optimize ${DDC_HIER_DESIGNS}
if { ${DDC_HIER_DESIGNS} != ""} {
  if {[shell_is_in_topographical_mode]} {
    # Hierarchical DDC (non-ILM) blocks must be marked as physical hierarchy
    set_physical_hierarchy [sub_instances_of -hierarchy -of_references ${DDC_HIER_DESIGNS} ${DESIGN_NAME}]
    get_physical_hierarchy
  } else {
    # Don't touch these blocks in DC-WLM
    set_dont_touch [get_designs ${DDC_HIER_DESIGNS}]
  }
}

# Prevent optimization of top-level logic based on physical block contents
# (required for hierarchical formal verification flow)
set HIER_DESIGNS "${DDC_HIER_DESIGNS} ${DC_ILM_HIER_DESIGNS} ${ICC_ILM_HIER_DESIGNS}"
set_boundary_optimization ${HIER_DESIGNS} false
set compile_preserve_subdesign_interfaces true

#################################################################################
# Apply Logical Design Constraints
#################################################################################

source -echo -verbose ${DESIGN_NAME}.constraints.tcl

# You can enable analysis and optimization for multiple clocks per register.
# To use this, you must constrain to remove false interactions between mutually exclusive
# clocks.  This is needed to prevent unnecessary analysis that can result in
# a significant runtime increase with this feature enabled.
#
# set_clock_groups -physically_exclusive | -logically_exclusive | -asynchronous \
#                  -group {CLKA, CLKB} -group {CLKC, CLKD} 
#
# set timing_enable_multiple_clocks_per_reg true


#################################################################################
# Apply Operating Conditions
#################################################################################

# Set operating condition on top level
# Comment out if these are already set in your constraints file.

set_operating_conditions -max <max_opcond> -min <min_opcond>

#################################################################################
# Create Default Path Groups
#
# Separating these paths can help improve optimization.
# Remove these path group settings if user path groups have already been defined.
#################################################################################

set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]] 
group_path -name REGOUT -to [all_outputs] 
group_path -name REGIN -from [remove_from_collection [all_inputs] $ports_clock_root] 
group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs]

#################################################################################
# Power Optimization Section
#################################################################################

    #############################################################################
    # Insert Clock Gating Logic
    #
    # set_clock_gating_style is now optional.  Default values will be used by
    # the tool.  Use this command with values suitable to your design style
    # to control the insertion of clock-gating logic.
    #############################################################################

    # Default clock_gating_style suits most designs.  Change only if necessary.
    # set_clock_gating_style ...

    # Clock gate insertion is now performed during compile_ultra -gate_clock
    # so insert_clock_gating is no longer recommended at this step.

    #############################################################################
    # Apply Power Optimization Constraints
    #############################################################################

    # Include a SAIF file, if possible, for power optimization.  If a SAIF file
    # is not provided, the default toggle rate of 0.1 will be used for propagating
    # switching activity.

    # read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose

    # Remove set_max_total_power power optimization constraint from scripts in 2008.09
    # Enable both of the following settings for total power optimization

    set_max_leakage_power 0
    # set_max_dynamic_power 0

    if {[shell_is_in_topographical_mode]} {
      # Setting power constraints will automatically enable power prediction using clock tree estimation.
      # If you are not setting any power constraints and you still want to report
      # correlated power, you can use the following command to turn on power prediction.

      # set_power_prediction true
    }

if {[shell_is_in_topographical_mode]} {

  ##################################################################################
  # Apply Physical Design Constraints
  #
  # Optional: Floorplan information can be read in here if available.
  # This is highly recommended for irregular floorplans.
  #
  # Floorplan constraints can be extracted from DEF files using
  # extract_physical_constraints OR provided from Tcl commands.
  #
  ##################################################################################

  # Specify ignored layers for routing to improve correlation
  # Use the same ignored layers that will be used during place and route

  if { ${MIN_ROUTING_LAYER} != ""} {
    set_ignored_layers -min_routing_layer ${MIN_ROUTING_LAYER}
  }
  if { ${MAX_ROUTING_LAYER} != ""} {
    set_ignored_layers -max_routing_layer ${MAX_ROUTING_LAYER}
  }

  report_ignored_layers

  # During DEF constraint extraction, extract_physical_constraints will attempt to
  # match DEF names back to precompile names in memory using standard matching rules.
  # Modify fuzzy_query_options if other characters are used for hierarchy separators
  # or bus names. 

  # set_fuzzy_query_options -hierarchical_separators {/ _ .} \
  #                         -bus_name_notations {[] __ ()} \
  #                         -class {cell pin port net} \
  #                         -show


  extract_physical_constraints ${DESIGN_NAME}.def
  
  # OR
  
  # source -echo -verbose ${DESIGN_NAME}.physical_constraints.tcl


  # If the macro names change after mapping and writing out the design due to
  # ungrouping or Verilog change_names renaming, it may be necessary to translate 
  # the names to correspond to the cell names that exist before compile.
  # The following is an example of how the translation can be performed using an
  # available Synopsys utility:  updateDesignDef.tcl
  #
  # This utility can be downloaded from Synopsys SolvNet at the following location:
  #   "Design Compiler Topographical Macro Name Translation Utility" 
  #    https://solvnet.synopsys.com/retrieve/019181.html
  #
  # Only perform this translation once, to save runtime.
    
  # For DEF:
  # This translation is done automatically by extract_physical_constraints

  # For Tcl (derive_physical_constraints from JupiterXT):
  # source updateDesignDef.tcl
  # updateTclMacroNames ${DESIGN_NAME}.physical_constraints.tcl ${DESIGN_NAME}.physical_constraints.dct.tcl
  # source -echo -verbose ${DESIGN_NAME}.physical_constraints.dct.tcl

  # You can also save the extracted constraints for fast loading next time.
  # write_physical_constraints -output ${DESIGN_NAME}.physical_constraints.tcl

  # Verify that all the desired physical constraints have been applied
  report_physical_constraints > ${REPORTS_DIR}/${DESIGN_NAME}.physical_constraints.rpt
}


#################################################################################
# Apply Additional Optimization Constraints
#################################################################################

# Prevent assignment statements in the Verilog netlist.
set_fix_multiple_port_nets -all -buffer_constants

#################################################################################
# Compile the Design
#
# Recommended Options:
#
#     -scan