lcdfinal.hif

LCD显示

Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
Reset_Delay
# storage
db|lcdfinal.(1).cnf
db|lcdfinal.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Reset_Delay.v
21768b2a4956d7b3426fdcbed5f8a2d
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Reset_Delay:r0
}
# macro_sequence

# end
# entity
LCD_Controller
# storage
db|lcdfinal.(3).cnf
db|lcdfinal.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_Controller.v
a1e9e32719c37c21943c1cc1e81b859
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
CLK_Divide
16
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
LCD_TEST_systemlocked:u3|LCD_Controller:u0
}
# macro_sequence

# end
# entity
test
# storage
db|lcdfinal.(2).cnf
db|lcdfinal.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
test.v
ddb4529ecc19f55302929f78f8a8dbb
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
test:t0
}
# macro_sequence

# end
# entity
LCD_TEST_initial
# storage
db|lcdfinal.(4).cnf
db|lcdfinal.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_TEST_initial.v
408d58ce82c16f4679a7e430629895f
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
LCD_INTIAL
0
PARAMETER_SIGNED_DEC
DEF
LCD_LINE1
5
PARAMETER_SIGNED_DEC
DEF
LCD_CH_LINE
21
PARAMETER_SIGNED_DEC
DEF
LCD_LINE2
22
PARAMETER_SIGNED_DEC
DEF
LUT_SIZE
38
PARAMETER_SIGNED_DEC
DEF
}
# macro_sequence

# end
# entity
lcdfinal
# storage
db|lcdfinal.(0).cnf
db|lcdfinal.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcdfinal.v
b775ab8a85f3ee3c933735cfae9880bb
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
LCD_TEST_systemlocked
# storage
db|lcdfinal.(5).cnf
db|lcdfinal.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCD_TEST_systemlocked.v
e21abe5dfab995f0be64f2fa7bd435f4
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
LCD_INTIAL
0
PARAMETER_SIGNED_DEC
DEF
LCD_LINE1
5
PARAMETER_SIGNED_DEC
DEF
LCD_CH_LINE
21
PARAMETER_SIGNED_DEC
DEF
LCD_LINE2
22
PARAMETER_SIGNED_DEC
DEF
LUT_SIZE
38
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
LCD_TEST_systemlocked:u3
}
# macro_sequence

# end
# complete