prev_cmp_lcdfinal.tan.qmsg

LCD显示

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register LCD_TEST_systemlocked:u3\|mDLY\[9\] register LCD_TEST_systemlocked:u3\|mDLY\[7\] 252.53 MHz 3.96 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 252.53 MHz between source register \"LCD_TEST_systemlocked:u3\|mDLY\[9\]\" and destination register \"LCD_TEST_systemlocked:u3\|mDLY\[7\]\" (period= 3.96 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.744 ns + Longest register register " "Info: + Longest register to register delay is 3.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST_systemlocked:u3\|mDLY\[9\] 1 REG LCFF_X44_Y20_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y20_N1; Fanout = 3; REG Node = 'LCD_TEST_systemlocked:u3\|mDLY\[9\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_TEST_systemlocked:u3|mDLY[9] } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.150 ns) 1.436 ns LCD_TEST_systemlocked:u3\|LessThan1~263 2 COMB LCCOMB_X43_Y20_N14 1 " "Info: 2: + IC(1.286 ns) + CELL(0.150 ns) = 1.436 ns; Loc. = LCCOMB_X43_Y20_N14; Fanout = 1; COMB Node = 'LCD_TEST_systemlocked:u3\|LessThan1~263'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.436 ns" { LCD_TEST_systemlocked:u3|mDLY[9] LCD_TEST_systemlocked:u3|LessThan1~263 } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.420 ns) 2.114 ns LCD_TEST_systemlocked:u3\|LessThan1~265 3 COMB LCCOMB_X43_Y20_N18 4 " "Info: 3: + IC(0.258 ns) + CELL(0.420 ns) = 2.114 ns; Loc. = LCCOMB_X43_Y20_N18; Fanout = 4; COMB Node = 'LCD_TEST_systemlocked:u3\|LessThan1~265'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.678 ns" { LCD_TEST_systemlocked:u3|LessThan1~263 LCD_TEST_systemlocked:u3|LessThan1~265 } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.150 ns) 2.533 ns LCD_TEST_systemlocked:u3\|LessThan1~266 4 COMB LCCOMB_X43_Y20_N28 18 " "Info: 4: + IC(0.269 ns) + CELL(0.150 ns) = 2.533 ns; Loc. = LCCOMB_X43_Y20_N28; Fanout = 18; COMB Node = 'LCD_TEST_systemlocked:u3\|LessThan1~266'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.419 ns" { LCD_TEST_systemlocked:u3|LessThan1~265 LCD_TEST_systemlocked:u3|LessThan1~266 } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.510 ns) 3.744 ns LCD_TEST_systemlocked:u3\|mDLY\[7\] 5 REG LCFF_X44_Y21_N29 3 " "Info: 5: + IC(0.701 ns) + CELL(0.510 ns) = 3.744 ns; Loc. = LCFF_X44_Y21_N29; Fanout = 3; REG Node = 'LCD_TEST_systemlocked:u3\|mDLY\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.211 ns" { LCD_TEST_systemlocked:u3|LessThan1~266 LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.230 ns ( 32.85 % ) " "Info: Total cell delay = 1.230 ns ( 32.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.514 ns ( 67.15 % ) " "Info: Total interconnect delay = 2.514 ns ( 67.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.744 ns" { LCD_TEST_systemlocked:u3|mDLY[9] LCD_TEST_systemlocked:u3|LessThan1~263 LCD_TEST_systemlocked:u3|LessThan1~265 LCD_TEST_systemlocked:u3|LessThan1~266 LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.744 ns" { LCD_TEST_systemlocked:u3|mDLY[9] {} LCD_TEST_systemlocked:u3|LessThan1~263 {} LCD_TEST_systemlocked:u3|LessThan1~265 {} LCD_TEST_systemlocked:u3|LessThan1~266 {} LCD_TEST_systemlocked:u3|mDLY[7] {} } { 0.000ns 1.286ns 0.258ns 0.269ns 0.701ns } { 0.000ns 0.150ns 0.420ns 0.150ns 0.510ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.679 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.025 ns) + CELL(0.537 ns) 2.679 ns LCD_TEST_systemlocked:u3\|mDLY\[7\] 3 REG LCFF_X44_Y21_N29 3 " "Info: 3: + IC(1.025 ns) + CELL(0.537 ns) = 2.679 ns; Loc. = LCFF_X44_Y21_N29; Fanout = 3; REG Node = 'LCD_TEST_systemlocked:u3\|mDLY\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.33 % ) " "Info: Total cell delay = 1.536 ns ( 57.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.143 ns ( 42.67 % ) " "Info: Total interconnect delay = 1.143 ns ( 42.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|mDLY[7] {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.681 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns LCD_TEST_systemlocked:u3\|mDLY\[9\] 3 REG LCFF_X44_Y20_N1 3 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X44_Y20_N1; Fanout = 3; REG Node = 'LCD_TEST_systemlocked:u3\|mDLY\[9\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[9] } "NODE_NAME" } } { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[9] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|mDLY[9] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|mDLY[7] {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[9] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|mDLY[9] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 76 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 76 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.744 ns" { LCD_TEST_systemlocked:u3|mDLY[9] LCD_TEST_systemlocked:u3|LessThan1~263 LCD_TEST_systemlocked:u3|LessThan1~265 LCD_TEST_systemlocked:u3|LessThan1~266 LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.744 ns" { LCD_TEST_systemlocked:u3|mDLY[9] {} LCD_TEST_systemlocked:u3|LessThan1~263 {} LCD_TEST_systemlocked:u3|LessThan1~265 {} LCD_TEST_systemlocked:u3|LessThan1~266 {} LCD_TEST_systemlocked:u3|mDLY[7] {} } { 0.000ns 1.286ns 0.258ns 0.269ns 0.701ns } { 0.000ns 0.150ns 0.420ns 0.150ns 0.510ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|mDLY[7] {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|mDLY[9] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|mDLY[9] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LCD_EN LCD_TEST_systemlocked:u3\|LCD_Controller:u0\|LCD_EN 9.549 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LCD_EN\" through register \"LCD_TEST_systemlocked:u3\|LCD_Controller:u0\|LCD_EN\" is 9.549 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.680 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.537 ns) 2.680 ns LCD_TEST_systemlocked:u3\|LCD_Controller:u0\|LCD_EN 3 REG LCFF_X45_Y21_N1 2 " "Info: 3: + IC(1.026 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X45_Y21_N1; Fanout = 2; REG Node = 'LCD_TEST_systemlocked:u3\|LCD_Controller:u0\|LCD_EN'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN } "NODE_NAME" } } { "LCD_Controller.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_Controller.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.31 % ) " "Info: Total cell delay = 1.536 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.144 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN {} } { 0.000ns 0.000ns 0.118ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "LCD_Controller.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_Controller.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.619 ns + Longest register pin " "Info: + Longest register to pin delay is 6.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_TEST_systemlocked:u3\|LCD_Controller:u0\|LCD_EN 1 REG LCFF_X45_Y21_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y21_N1; Fanout = 2; REG Node = 'LCD_TEST_systemlocked:u3\|LCD_Controller:u0\|LCD_EN'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN } "NODE_NAME" } } { "LCD_Controller.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_Controller.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.987 ns) + CELL(2.632 ns) 6.619 ns LCD_EN 2 PIN PIN_K3 0 " "Info: 2: + IC(3.987 ns) + CELL(2.632 ns) = 6.619 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'LCD_EN'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.619 ns" { LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN LCD_EN } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 39.76 % ) " "Info: Total cell delay = 2.632 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.987 ns ( 60.24 % ) " "Info: Total interconnect delay = 3.987 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.619 ns" { LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN LCD_EN } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.619 ns" { LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN {} LCD_EN {} } { 0.000ns 3.987ns } { 0.000ns 2.632ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { CLOCK_50 CLOCK_50~clkctrl LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN {} } { 0.000ns 0.000ns 0.118ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.619 ns" { LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN LCD_EN } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.619 ns" { LCD_TEST_systemlocked:u3|LCD_Controller:u0|LCD_EN {} LCD_EN {} } { 0.000ns 3.987ns } { 0.000ns 2.632ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Peak virtual memory: 133 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 18 14:46:56 2009 " "Info: Processing ended: Wed Feb 18 14:46:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}