prev_cmp_lcdfinal.qmsg

LCD显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 18 15:46:08 2009 " "Info: Processing started: Wed Feb 18 15:46:08 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "LCD_XX lcdfinal.v(57) " "Error (10149): Verilog HDL Declaration error at lcdfinal.v(57): identifier \"LCD_XX\" is already declared in the present scope" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 57 0 0 } }  } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lcdfinal lcdfinal.v(5) " "Error (10112): Ignored design unit \"lcdfinal\" at lcdfinal.v(5) due to previous errors" {  } { { "lcdfinal.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal.v" 5 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdfinal.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file lcdfinal.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_welcomlock " "Info: Found entity 1: LCD_TEST_welcomlock" {  } { { "LCD_TEST.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_Controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Controller " "Info: Found entity 1: LCD_Controller" {  } { { "LCD_Controller.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_Controller.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCDmodule.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCDmodule.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCDmodule " "Info: Found entity 1: LCDmodule" {  } { { "LCDmodule.v" "" { Text "F:/jeffie/final/lcdfinal/LCDmodule.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reset_Delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "Reset_Delay.v" "" { Text "F:/jeffie/final/lcdfinal/Reset_Delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "choose.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file choose.v" { { "Info" "ISGN_ENTITY_NAME" "1 choose " "Info: Found entity 1: choose" {  } { { "choose.v" "" { Text "F:/jeffie/final/lcdfinal/choose.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.v" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.v" "" { Text "F:/jeffie/final/lcdfinal/test.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/jeffie/final/lcdfinal/LCD_TEST_welcomlock.v " "Warning: Can't analyze file -- file F:/jeffie/final/lcdfinal/LCD_TEST_welcomlock.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_open.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_open.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_open " "Info: Found entity 1: LCD_TEST_open" {  } { { "LCD_TEST_open.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_open.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_wrong.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_wrong.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_wrong " "Info: Found entity 1: LCD_TEST_wrong" {  } { { "LCD_TEST_wrong.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_wrong.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_systemlocked.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_systemlocked.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_systemlocked " "Info: Found entity 1: LCD_TEST_systemlocked" {  } { { "LCD_TEST_systemlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_systemlocked.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_welcomlocked.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_welcomlocked.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_welcomlocked " "Info: Found entity 1: LCD_TEST_welcomlocked" {  } { { "LCD_TEST_welcomlocked.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_welcomlocked.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_TEST_initial.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file LCD_TEST_initial.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_TEST_initial " "Info: Found entity 1: LCD_TEST_initial" {  } { { "LCD_TEST_initial.v" "" { Text "F:/jeffie/final/lcdfinal/LCD_TEST_initial.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "DLY_RST lcdfinal1.v(103) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(103): created implicit net for \"DLY_RST\"" {  } { { "lcdfinal1.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal1.v" 103 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "LCD_DATA lcdfinal1.v(105) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(105): created implicit net for \"LCD_DATA\"" {  } { { "lcdfinal1.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal1.v" 105 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "LCD_RW lcdfinal1.v(106) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(106): created implicit net for \"LCD_RW\"" {  } { { "lcdfinal1.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal1.v" 106 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "LCD_EN lcdfinal1.v(107) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(107): created implicit net for \"LCD_EN\"" {  } { { "lcdfinal1.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal1.v" 107 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "LCD_RS lcdfinal1.v(108) " "Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(108): created implicit net for \"LCD_RS\"" {  } { { "lcdfinal1.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal1.v" 108 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdfinal1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcdfinal1.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcdfinal1 " "Info: Found entity 1: lcdfinal1" {  } { { "lcdfinal1.v" "" { Text "F:/jeffie/final/lcdfinal/lcdfinal1.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdfinal.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcdfinal.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcdfinal " "Info: Found entity 1: lcdfinal" {  } { { "lcdfinal.bdf" "" { Schematic "F:/jeffie/final/lcdfinal/lcdfinal.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 6 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 6 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Error: Peak virtual memory: 160 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 18 15:46:11 2009 " "Error: Processing ended: Wed Feb 18 15:46:11 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 6 s " "Error: Quartus II Full Compilation was unsuccessful. 4 errors, 6 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}