📄 lcdfinal.map.rpt
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Analysis & Synthesis report for lcdfinal
Wed Feb 18 15:46:24 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed Feb 18 15:46:24 2009 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; lcdfinal ;
; Top-level Entity Name ; lcdfinal ;
; Family ; Cyclone II ;
; Total logic elements ; N/A until Partition Merge ;
; Total combinational functions ; N/A until Partition Merge ;
; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; N/A until Partition Merge ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
+------------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; lcdfinal ; lcdfinal ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+--------------------------------------------------------------+--------------------+--------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Wed Feb 18 15:46:22 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcdfinal -c lcdfinal
Info: Found 1 design units, including 1 entities, in source file lcdfinal.v
Info: Found entity 1: lcdfinal
Info: Found 1 design units, including 1 entities, in source file LCD_TEST.v
Info: Found entity 1: LCD_TEST_welcomlock
Info: Found 1 design units, including 1 entities, in source file LCD_Controller.v
Info: Found entity 1: LCD_Controller
Info: Found 1 design units, including 1 entities, in source file LCDmodule.v
Info: Found entity 1: LCDmodule
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
Info: Found entity 1: Reset_Delay
Info: Found 1 design units, including 1 entities, in source file choose.v
Info: Found entity 1: choose
Info: Found 1 design units, including 1 entities, in source file test.v
Info: Found entity 1: test
Warning: Can't analyze file -- file F:/jeffie/final/lcdfinal/LCD_TEST_welcomlock.v is missing
Info: Found 1 design units, including 1 entities, in source file LCD_TEST_open.v
Info: Found entity 1: LCD_TEST_open
Info: Found 1 design units, including 1 entities, in source file LCD_TEST_wrong.v
Info: Found entity 1: LCD_TEST_wrong
Info: Found 1 design units, including 1 entities, in source file LCD_TEST_systemlocked.v
Info: Found entity 1: LCD_TEST_systemlocked
Info: Found 1 design units, including 1 entities, in source file LCD_TEST_welcomlocked.v
Info: Found entity 1: LCD_TEST_welcomlocked
Info: Found 1 design units, including 1 entities, in source file LCD_TEST_initial.v
Info: Found entity 1: LCD_TEST_initial
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(103): created implicit net for "DLY_RST"
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(105): created implicit net for "LCD_DATA"
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(106): created implicit net for "LCD_RW"
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(107): created implicit net for "LCD_EN"
Warning (10236): Verilog HDL Implicit Net warning at lcdfinal1.v(108): created implicit net for "LCD_RS"
Info: Found 1 design units, including 1 entities, in source file lcdfinal1.v
Info: Found entity 1: lcdfinal1
Error: Can't compile duplicate declarations of entity "lcdfinal" into library "work"
Error: Found entity "lcdfinal" in file lcdfinal.v File: F:/jeffie/final/lcdfinal/lcdfinal.v Line: 5
Error: Found entity "lcdfinal" in file lcdfinal.bdf
Info: Found 1 design units, including 1 entities, in source file lcdfinal.bdf
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 6 warnings
Error: Peak virtual memory: 160 megabytes
Error: Processing ended: Wed Feb 18 15:46:25 2009
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:02
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