lcd_demo.vhd

一种基于FPGA和quartusII技术开发的彩色LED显示测试程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use	ieee.std_logic_unsigned.all;


ENTITY lcd_demo IS
	PORT
	(
		 clk,CCLK : IN STD_LOGIC;
		LCDR : OUT STD_LOGIC_VECTOR(5 downto 0);
		LCDG : OUT STD_LOGIC_VECTOR(5 downto 0);
		LCDB : OUT STD_LOGIC_VECTOR(5 downto 0);
		TLED : out std_logic;
		LCDDE,LCDCLK : OUT STD_LOGIC
	);
	
END lcd_demo;

ARCHITECTURE rtl OF lcd_demo IS
	constant HACTIVE : integer := 800;
	constant VACTIVE : integer := 480;
	constant HSCANL : integer := 1026;
	constant VSCANL : integer := 506;
	
	signal hcnt : std_logic_vector(10 downto 0);
	signal vcnt : std_logic_vector(9 downto 0);
	signal hs : std_logic;
	signal vs : std_logic;
	signal CNT6A : std_logic_vector(2 downto 0);
	signal CNTC : std_logic_vector(5 downto 0);
	signal tcnt : std_logic_vector(24 downto 0);

	
BEGIN

process(clk) begin
	if rising_edge(clk) then
		if hcnt < HACTIVE then 
			hs <= '1';
		else
			hs <= '0';
		end if;
	end if;
	end process;
	
	process(clk) begin
	if rising_edge(clk) then
		if vcnt < VACTIVE then 
			vs <= '1';
		else
			vs <= '0';
		end if;
	end if;
end process;

process(clk) begin
	if rising_edge(clk) then
		if hcnt < HSCANL then 
			hcnt <= hcnt + 1;
		else
			hcnt <= (others => '0');
		end if;
	end if;
end process;

process(clk) begin
	if rising_edge(clk) then
		if hcnt = HACTIVE-1 then 
			if vcnt < VSCANL then
				vcnt <= vcnt + 1;
			else
				vcnt <= (others => '0');
			end if;
		end if;
	end if;
end process;

process(CCLK) begin
	if rising_edge(CCLK) then
		CNT6A <= CNT6A + 1; 
	end if;
end process;

process(CCLK) begin
	if rising_edge(CCLK) then
	CNTC <= CNTC + 5; 
	end if;
end process;

PROCESS( CNT6A )
  BEGIN
  CASE  CNT6A  IS
   WHEN "000" =>  LCDR<= hcnt(10 downto 7)& CNTC(1 DOWNTO 0) ;   LCDG<= vcnt(3 downto 0)& CNTC(1 DOWNTO 0);  LCDB<= hcnt(3 downto 0)& CNTC(2 DOWNTO 1);  
   WHEN "001" =>  LCDR<= hcnt(9 downto 6)& CNTC(2 DOWNTO 1);   LCDG<= vcnt(4 downto 1)& CNTC(2 DOWNTO 1);    LCDB<= hcnt(4 downto 1)& CNTC(3 DOWNTO 2) ;  
   WHEN "010" =>  LCDR<= hcnt(8 downto 5)& CNTC(3 DOWNTO 2);  LCDG<= vcnt(5 downto 2)& CNTC(3 DOWNTO 2);     LCDB<= hcnt(5 downto 2)& CNTC(4 DOWNTO 3) ;  
   WHEN "011" =>  LCDR<= hcnt(7 downto 4)& CNTC(4 DOWNTO 3);   LCDG<= vcnt(6 downto 3)& CNTC(4 DOWNTO 3);    LCDB<= hcnt(6 downto 3)& CNTC(5 DOWNTO 4) ;  
   WHEN "100" =>  LCDR<= hcnt(6 downto 3)& CNTC(5 DOWNTO 4);   LCDG<= vcnt(7 downto 4)& CNTC(5 DOWNTO 4);    LCDB<= hcnt(7 downto 4)& CNTC(4 DOWNTO 3) ;  
   WHEN "101" =>  LCDR<= CNTC(1 DOWNTO 0)& hcnt(5 downto 2) ;   LCDG<= vcnt(8 downto 5)& CNTC(1 DOWNTO 0);   LCDB<= hcnt(8 downto 5)& CNTC(3 DOWNTO 2) ;  
   WHEN "110" =>  LCDR<=  CNTC(2 DOWNTO 1)& hcnt(4 downto 1);   LCDG<= vcnt(9 downto 6)& CNTC(2 DOWNTO 1);   LCDB<= hcnt(9 downto 6)& CNTC(2 DOWNTO 1) ;  
   WHEN "111" =>  LCDR<= CNTC(3 DOWNTO 2)& hcnt(3 downto 0);   LCDG<= vcnt(3 downto 0)& CNTC(3 DOWNTO 2);   LCDB<= hcnt(10 downto 7)& CNTC(1 DOWNTO 0) ;  
   WHEN OTHERS =>  NULL ;
   END CASE ;
  END PROCESS ;
  


lcdde <=  (hs and vs);



LCDCLK <= clk;

process(clk) begin
	if rising_edge(clk) then
		tcnt <= tcnt + 1;
	end if;
end process;

TLED <= tcnt(tcnt'HIGH);


END rtl;