📄 dds_vhdl.tan.rpt
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; 9.811 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[27] ; REG10B:u5|DOUT[7] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 3.261 ns ;
; 9.811 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[27] ; REG10B:u5|DOUT[8] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 3.261 ns ;
; 9.811 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[27] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 3.261 ns ;
; 10.030 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[27] ; REG10B:u5|DOUT[6] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 3.042 ns ;
; 10.231 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[28] ; REG10B:u5|DOUT[7] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.841 ns ;
; 10.231 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[28] ; REG10B:u5|DOUT[8] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.841 ns ;
; 10.231 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[28] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.841 ns ;
; 10.302 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[26] ; REG10B:u5|DOUT[7] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.770 ns ;
; 10.302 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[26] ; REG10B:u5|DOUT[8] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.770 ns ;
; 10.302 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[26] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.770 ns ;
; 10.451 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[27] ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg5 ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.027 ns ; 2.576 ns ;
; 10.476 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[24] ; REG10B:u5|DOUT[7] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.596 ns ;
; 10.476 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[24] ; REG10B:u5|DOUT[8] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.596 ns ;
; 10.476 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[24] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.596 ns ;
; 10.478 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[29] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.594 ns ;
; 10.521 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[26] ; REG10B:u5|DOUT[6] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.551 ns ;
; 10.558 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[29] ; REG10B:u5|DOUT[8] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.514 ns ;
; 10.569 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; REG32B:u2|DOUT[31] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.503 ns ;
; 10.589 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[30] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.483 ns ;
; 10.601 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[26] ; REG10B:u5|DOUT[5] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.471 ns ;
; 10.644 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; REG32B:u2|DOUT[31] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.428 ns ;
; 10.646 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; REG32B:u2|DOUT[26] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.426 ns ;
; 10.646 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; REG32B:u2|DOUT[27] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.426 ns ;
; 10.646 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; REG32B:u2|DOUT[28] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.426 ns ;
; 10.646 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; REG32B:u2|DOUT[29] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.426 ns ;
; 10.646 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; REG32B:u2|DOUT[30] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.426 ns ;
; 10.654 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[27] ; REG10B:u5|DOUT[5] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.418 ns ;
; 10.671 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[21] ; REG32B:u2|DOUT[31] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.401 ns ;
; 10.678 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg0 ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.027 ns ; 2.349 ns ;
; 10.689 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[24] ; REG10B:u5|DOUT[6] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.383 ns ;
; 10.717 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[25] ; REG10B:u5|DOUT[7] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.355 ns ;
; 10.717 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[25] ; REG10B:u5|DOUT[8] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.355 ns ;
; 10.717 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[25] ; REG10B:u5|DOUT[9] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.355 ns ;
; 10.719 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[22] ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg0 ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.027 ns ; 2.308 ns ;
; 10.721 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; REG32B:u2|DOUT[26] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.351 ns ;
; 10.721 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; REG32B:u2|DOUT[27] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.351 ns ;
; 10.721 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; REG32B:u2|DOUT[28] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.351 ns ;
; 10.721 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; REG32B:u2|DOUT[29] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.351 ns ;
; 10.721 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; REG32B:u2|DOUT[30] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.351 ns ;
; 10.725 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[25] ; REG32B:u2|DOUT[31] ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.072 ns ; 2.347 ns ;
; 10.729 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[23] ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg1 ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.027 ns ; 2.298 ns ;
; 10.745 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; REG32B:u2|DOUT[30] ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg8 ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns ; 13.027 ns ; 2.282 ns ;
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