dds_vhdl.fit.eqn

来自「好好的学习资料」· EQN 代码 · 共 714 行 · 第 1/5 页

--S1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[9] at M4K_X19_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
S1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[9]_PORT_A_data_in_reg = DFFE(S1_q_a[9]_PORT_A_data_in, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_a[9]_PORT_B_data_in_reg = DFFE(S1_q_a[9]_PORT_B_data_in, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[9]_PORT_A_address_reg = DFFE(S1_q_a[9]_PORT_A_address, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[9]_PORT_B_address_reg = DFFE(S1_q_a[9]_PORT_B_address, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_write_enable = GND;
S1_q_a[9]_PORT_A_write_enable_reg = DFFE(S1_q_a[9]_PORT_A_write_enable, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_write_enable = T1L72;
S1_q_a[9]_PORT_B_write_enable_reg = DFFE(S1_q_a[9]_PORT_B_write_enable, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_a[9]_clock_1 = GLOBAL(A1L5);
S1_q_a[9]_PORT_A_data_out = MEMORY(S1_q_a[9]_PORT_A_data_in_reg, S1_q_a[9]_PORT_B_data_in_reg, S1_q_a[9]_PORT_A_address_reg, S1_q_a[9]_PORT_B_address_reg, S1_q_a[9]_PORT_A_write_enable_reg, S1_q_a[9]_PORT_B_write_enable_reg, , , S1_q_a[9]_clock_0, S1_q_a[9]_clock_1, , , , );
S1_q_a[9] = S1_q_a[9]_PORT_A_data_out[0];

--S1_q_b[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[9] at M4K_X19_Y13
S1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[9]_PORT_A_data_in_reg = DFFE(S1_q_b[9]_PORT_A_data_in, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_b[9]_PORT_B_data_in_reg = DFFE(S1_q_b[9]_PORT_B_data_in, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[9]_PORT_A_address_reg = DFFE(S1_q_b[9]_PORT_A_address, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[9]_PORT_B_address_reg = DFFE(S1_q_b[9]_PORT_B_address, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_write_enable = GND;
S1_q_b[9]_PORT_A_write_enable_reg = DFFE(S1_q_b[9]_PORT_A_write_enable, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_write_enable = T1L72;
S1_q_b[9]_PORT_B_write_enable_reg = DFFE(S1_q_b[9]_PORT_B_write_enable, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_b[9]_clock_1 = GLOBAL(A1L5);
S1_q_b[9]_PORT_B_data_out = MEMORY(S1_q_b[9]_PORT_A_data_in_reg, S1_q_b[9]_PORT_B_data_in_reg, S1_q_b[9]_PORT_A_address_reg, S1_q_b[9]_PORT_B_address_reg, S1_q_b[9]_PORT_A_write_enable_reg, S1_q_b[9]_PORT_B_write_enable_reg, , , S1_q_b[9]_clock_0, S1_q_b[9]_clock_1, , , , );
S1_q_b[9] = S1_q_b[9]_PORT_B_data_out[0];

--S1_q_a[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[0] at M4K_X19_Y13
S1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[9]_PORT_A_data_in_reg = DFFE(S1_q_a[9]_PORT_A_data_in, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_a[9]_PORT_B_data_in_reg = DFFE(S1_q_a[9]_PORT_B_data_in, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[9]_PORT_A_address_reg = DFFE(S1_q_a[9]_PORT_A_address, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[9]_PORT_B_address_reg = DFFE(S1_q_a[9]_PORT_B_address, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_write_enable = GND;
S1_q_a[9]_PORT_A_write_enable_reg = DFFE(S1_q_a[9]_PORT_A_write_enable, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_write_enable = T1L72;
S1_q_a[9]_PORT_B_write_enable_reg = DFFE(S1_q_a[9]_PORT_B_write_enable, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_a[9]_clock_1 = GLOBAL(A1L5);
S1_q_a[9]_PORT_A_data_out = MEMORY(S1_q_a[9]_PORT_A_data_in_reg, S1_q_a[9]_PORT_B_data_in_reg, S1_q_a[9]_PORT_A_address_reg, S1_q_a[9]_PORT_B_address_reg, S1_q_a[9]_PORT_A_write_enable_reg, S1_q_a[9]_PORT_B_write_enable_reg, , , S1_q_a[9]_clock_0, S1_q_a[9]_clock_1, , , , );
S1_q_a[0] = S1_q_a[9]_PORT_A_data_out[3];

--S1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2] at M4K_X19_Y13
S1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[9]_PORT_A_data_in_reg = DFFE(S1_q_a[9]_PORT_A_data_in, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_a[9]_PORT_B_data_in_reg = DFFE(S1_q_a[9]_PORT_B_data_in, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[9]_PORT_A_address_reg = DFFE(S1_q_a[9]_PORT_A_address, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[9]_PORT_B_address_reg = DFFE(S1_q_a[9]_PORT_B_address, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_write_enable = GND;
S1_q_a[9]_PORT_A_write_enable_reg = DFFE(S1_q_a[9]_PORT_A_write_enable, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_write_enable = T1L72;
S1_q_a[9]_PORT_B_write_enable_reg = DFFE(S1_q_a[9]_PORT_B_write_enable, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_a[9]_clock_1 = GLOBAL(A1L5);
S1_q_a[9]_PORT_A_data_out = MEMORY(S1_q_a[9]_PORT_A_data_in_reg, S1_q_a[9]_PORT_B_data_in_reg, S1_q_a[9]_PORT_A_address_reg, S1_q_a[9]_PORT_B_address_reg, S1_q_a[9]_PORT_A_write_enable_reg, S1_q_a[9]_PORT_B_write_enable_reg, , , S1_q_a[9]_clock_0, S1_q_a[9]_clock_1, , , , );
S1_q_a[2] = S1_q_a[9]_PORT_A_data_out[2];

--S1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[4] at M4K_X19_Y13
S1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_a[9]_PORT_A_data_in_reg = DFFE(S1_q_a[9]_PORT_A_data_in, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_a[9]_PORT_B_data_in_reg = DFFE(S1_q_a[9]_PORT_B_data_in, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_a[9]_PORT_A_address_reg = DFFE(S1_q_a[9]_PORT_A_address, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_a[9]_PORT_B_address_reg = DFFE(S1_q_a[9]_PORT_B_address, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_write_enable = GND;
S1_q_a[9]_PORT_A_write_enable_reg = DFFE(S1_q_a[9]_PORT_A_write_enable, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_write_enable = T1L72;
S1_q_a[9]_PORT_B_write_enable_reg = DFFE(S1_q_a[9]_PORT_B_write_enable, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_a[9]_clock_1 = GLOBAL(A1L5);
S1_q_a[9]_PORT_A_data_out = MEMORY(S1_q_a[9]_PORT_A_data_in_reg, S1_q_a[9]_PORT_B_data_in_reg, S1_q_a[9]_PORT_A_address_reg, S1_q_a[9]_PORT_B_address_reg, S1_q_a[9]_PORT_A_write_enable_reg, S1_q_a[9]_PORT_B_write_enable_reg, , , S1_q_a[9]_clock_0, S1_q_a[9]_clock_1, , , , );
S1_q_a[4] = S1_q_a[9]_PORT_A_data_out[1];

--S1_q_b[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[0] at M4K_X19_Y13
S1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[9]_PORT_A_data_in_reg = DFFE(S1_q_b[9]_PORT_A_data_in, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_b[9]_PORT_B_data_in_reg = DFFE(S1_q_b[9]_PORT_B_data_in, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[9]_PORT_A_address_reg = DFFE(S1_q_b[9]_PORT_A_address, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[9]_PORT_B_address_reg = DFFE(S1_q_b[9]_PORT_B_address, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_write_enable = GND;
S1_q_b[9]_PORT_A_write_enable_reg = DFFE(S1_q_b[9]_PORT_A_write_enable, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_write_enable = T1L72;
S1_q_b[9]_PORT_B_write_enable_reg = DFFE(S1_q_b[9]_PORT_B_write_enable, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_b[9]_clock_1 = GLOBAL(A1L5);
S1_q_b[9]_PORT_B_data_out = MEMORY(S1_q_b[9]_PORT_A_data_in_reg, S1_q_b[9]_PORT_B_data_in_reg, S1_q_b[9]_PORT_A_address_reg, S1_q_b[9]_PORT_B_address_reg, S1_q_b[9]_PORT_A_write_enable_reg, S1_q_b[9]_PORT_B_write_enable_reg, , , S1_q_b[9]_clock_0, S1_q_b[9]_clock_1, , , , );
S1_q_b[0] = S1_q_b[9]_PORT_B_data_out[3];

--S1_q_b[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[2] at M4K_X19_Y13
S1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[9]_PORT_A_data_in_reg = DFFE(S1_q_b[9]_PORT_A_data_in, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_b[9]_PORT_B_data_in_reg = DFFE(S1_q_b[9]_PORT_B_data_in, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[9]_PORT_A_address_reg = DFFE(S1_q_b[9]_PORT_A_address, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[9]_PORT_B_address_reg = DFFE(S1_q_b[9]_PORT_B_address, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_write_enable = GND;
S1_q_b[9]_PORT_A_write_enable_reg = DFFE(S1_q_b[9]_PORT_A_write_enable, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_write_enable = T1L72;
S1_q_b[9]_PORT_B_write_enable_reg = DFFE(S1_q_b[9]_PORT_B_write_enable, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_clock_0 = GLOBAL(X1__clk0);
S1_q_b[9]_clock_1 = GLOBAL(A1L5);
S1_q_b[9]_PORT_B_data_out = MEMORY(S1_q_b[9]_PORT_A_data_in_reg, S1_q_b[9]_PORT_B_data_in_reg, S1_q_b[9]_PORT_A_address_reg, S1_q_b[9]_PORT_B_address_reg, S1_q_b[9]_PORT_A_write_enable_reg, S1_q_b[9]_PORT_B_write_enable_reg, , , S1_q_b[9]_clock_0, S1_q_b[9]_clock_1, , , , );
S1_q_b[2] = S1_q_b[9]_PORT_B_data_out[2];

--S1_q_b[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[4] at M4K_X19_Y13
S1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
S1_q_b[9]_PORT_A_data_in_reg = DFFE(S1_q_b[9]_PORT_A_data_in, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_data_in = BUS(T1_ram_rom_data_reg[9], T1_ram_rom_data_reg[4], T1_ram_rom_data_reg[2], T1_ram_rom_data_reg[0]);
S1_q_b[9]_PORT_B_data_in_reg = DFFE(S1_q_b[9]_PORT_B_data_in, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_address = BUS(G1_DOUT[0], G1_DOUT[1], G1_DOUT[2], G1_DOUT[3], G1_DOUT[4], G1_DOUT[5], G1_DOUT[6], G1_DOUT[7], G1_DOUT[8], G1_DOUT[9]);
S1_q_b[9]_PORT_A_address_reg = DFFE(S1_q_b[9]_PORT_A_address, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_address = BUS(V1_safe_q[0], V1_safe_q[1], V1_safe_q[2], V1_safe_q[3], V1_safe_q[4], V1_safe_q[5], V1_safe_q[6], V1_safe_q[7], V1_safe_q[8], V1_safe_q[9]);
S1_q_b[9]_PORT_B_address_reg = DFFE(S1_q_b[9]_PORT_B_address, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_write_enable = GND;
S1_q_b[9]_PORT_A_write_enable_reg = DFFE(S1_q_b[9]_PORT_A_write_enable, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_write_enable = T1L72;
S1_q_b[9]_PORT_B_write_enable_reg = DFFE(S1_q_b[9]_PORT_B_write_enable, S1_q_b[9]_clock_1, , , );