dds_vhdl.tan.rpt

好好的学习资料

; Clock Setup: 'PLL20:u7|altpll:altpll_component|_clk0' ; 8.257 ns ; 75.00 MHz ( period = 13.333 ns ) ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg0  ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg0 ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'           ; N/A      ; None                             ; 79.73 MHz ( period = 12.542 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[1]                                                                                   ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                   ; altera_internal_jtag~TCKUTAP           ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Total number of failed paths                          ;          ;                                  ;                                  ;                                                                                                                                      ;                                                                                                                                     ;                                        ;                                        ; 0            ;
+-------------------------------------------------------+----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                           ;
+----------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; Clock Node Name                        ; Clock Setting Name ; Type       ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ;
+----------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; PLL20:u7|altpll:altpll_component|_clk0 ;                    ; PLL output ; 75.0 MHz         ; CLKK     ; 15                    ; 4                   ; -2.054 ns ;
; CLKK                                   ;                    ; User Pin   ; 20.0 MHz         ; NONE     ; N/A                   ; N/A                 ; N/A       ;
; altera_internal_jtag~TCKUTAP           ;                    ; User Pin   ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A       ;
+----------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLL20:u7|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-----------+-----------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack     ; Actual fmax (period)                          ; From                                                                                                                                ; To                                                                                                                                   ; From Clock                             ; To Clock                               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg0  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg1  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg2  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg3  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_datain_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_memory_reg0  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_datain_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_memory_reg1  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_datain_reg2 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_memory_reg2  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_datain_reg3 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_memory_reg3  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a6~porta_datain_reg0 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a6~porta_memory_reg0  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a6~porta_datain_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a6~porta_memory_reg1  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg0 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg0  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg1 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg1  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg2 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg2  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_datain_reg3 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_memory_reg3  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_datain_reg0 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_memory_reg0  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_datain_reg1 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_memory_reg1  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_datain_reg2 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_memory_reg2  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_datain_reg3 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_memory_reg3  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a4~porta_datain_reg0 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a4~porta_memory_reg0  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;
; 8.257 ns  ; 197.01 MHz ( period = 5.076 ns )              ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a4~porta_datain_reg1 ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a4~porta_memory_reg1  ; PLL20:u7|altpll:altpll_component|_clk0 ; PLL20:u7|altpll:altpll_component|_clk0 ; 13.333 ns                   ; 12.576 ns                 ; 4.319 ns                ;