dds_vhdl.map.rpt

好好的学习资料

+-----------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+---------------------+
; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 1024         ; 10           ; 1024         ; 10           ; 10240 ; ./data/LUT10X10.mif ;
; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 1024         ; 10           ; 1024         ; 10           ; 10240 ; ./data/LUT10X10.mif ;
+-----------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+---------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat Sep 03 15:18:34 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DDS_VHDL -c dds_vhdl
Info: Found 2 design units, including 1 entities, in source file adder32b.vhd
    Info: Found design unit 1: ADDER32B-behav
    Info: Found entity 1: ADDER32B
Info: Found 2 design units, including 1 entities, in source file dds_vhdl.vhd
    Info: Found design unit 1: DDS_VHDL-one
    Info: Found entity 1: DDS_VHDL
Info: Found 2 design units, including 1 entities, in source file reg32b.vhd
    Info: Found design unit 1: REG32B-behav
    Info: Found entity 1: REG32B
Info: Found 2 design units, including 1 entities, in source file sin_rom.vhd
    Info: Found design unit 1: sin_rom-SYN
    Info: Found entity 1: sin_rom
Info: Found 2 design units, including 1 entities, in source file adder10b.vhd
    Info: Found design unit 1: ADDER10B-behav
    Info: Found entity 1: ADDER10B
Info: Found 2 design units, including 1 entities, in source file reg10b.vhd
    Info: Found design unit 1: REG10B-behav
    Info: Found entity 1: REG10B
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_m9t.tdf
    Info: Found entity 1: altsyncram_m9t
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t5b2.tdf
    Info: Found entity 1: altsyncram_t5b2
Info: Found 3 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Using design file PLL20.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: PLL20-SYN
    Info: Found entity 1: PLL20
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Found 6 design units, including 2 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf
    Info: Found entity 1: decode_9ie
Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Duplicate registers merged to single register
    Info: Duplicate register REG32B:u2|DOUT[0] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[1] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[2] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[3] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[4] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[5] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[6] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[7] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[8] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[9] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[10] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[11] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[12] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[13] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[14] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[15] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[16] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[17] merged to single register REG32B:u2|DOUT[19]
    Info: Duplicate register REG32B:u2|DOUT[18] merged to single register REG32B:u2|DOUT[19]
Warning: Reduced register REG32B:u2|DOUT[19] with stuck data_in port to stuck value GND
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~60
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~8
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~60
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~8
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_kv8.tdf
    Info: Found entity 1: cntr_kv8
Info: Found 1 design units, including 1 entities, in source file db/cntr_pd8.tdf
    Info: Found entity 1: cntr_pd8
Info: Registers with preset signals will power-up high
Warning: Output port clk0 of PLL PLL20:u7|altpll:altpll_component|pll feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance.
Info: Implemented 350 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 22 output pins
    Info: Implemented 286 logic cells
    Info: Implemented 20 RAM segments
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Sep 03 15:18:50 2005
    Info: Elapsed time: 00:00:15