📄 dds_vhdl.map.rpt
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; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 22:1 ; 4 bits ; 56 LEs ; 48 LEs ; 8 LEs ; Yes ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 22:1 ; 4 bits ; 56 LEs ; 48 LEs ; 8 LEs ; Yes ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 10 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] ;
; 26:1 ; 4 bits ; 68 LEs ; 40 LEs ; 28 LEs ; Yes ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |DDS_VHDL|sld_hub:sld_hub_inst|NODE_ENA~0 ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |DDS_VHDL|sld_hub:sld_hub_inst|SHADOW_IRF_ENABLE[2] ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |DDS_VHDL|sld_hub:sld_hub_inst|IR_MUX_SEL[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 74 ;
; Number of synthesis-generated cells ; 212 ;
; Number of WYSIWYG LUTs ; 74 ;
; Number of synthesis-generated LUTs ; 167 ;
; Number of WYSIWYG registers ; 59 ;
; Number of synthesis-generated registers ; 124 ;
; Number of cells with combinational logic only ; 103 ;
; Number of cells with registers only ; 45 ;
; Number of cells with combinational logic and registers ; 138 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 8 ;
; Number of registers using Synchronous Load ; 31 ;
; Number of registers using Asynchronous Clear ; 117 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 128 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode ; Hierarchy Location ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------------------+
; 0 ; rom1 ; 10 ; 1024 ; Read/Write ; |DDS_VHDL|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated ;
; 1 ; rom1 ; 10 ; 1024 ; Read/Write ; |DDS_VHDL|sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------------------+
+-----------+
; Hierarchy ;
+-----------+
DDS_VHDL
|-- sld_hub:sld_hub_inst
|-- sld_dffex:\GEN_IRF:1:IRF
|-- sld_dffex:\GEN_IRF:2:IRF
|-- sld_dffex:\GEN_SHADOW_IRF:1:S_IRF
|-- sld_dffex:\GEN_SHADOW_IRF:2:S_IRF
|-- sld_dffex:BROADCAST
|-- sld_rom_sr:HUB_INFO_REG
|-- lpm_decode:instruction_decoder
|-- decode_9ie:auto_generated
|-- sld_dffex:IRF_ENA
|-- sld_dffex:IRF_ENA_0
|-- sld_dffex:IRSR
|-- lpm_shiftreg:jtag_ir_register
|-- sld_jtag_state_machine:jtag_state_machine
|-- sld_dffex:RESET
|-- ADDER32B:u1
|-- REG32B:u2
|-- sin_rom:u3
|-- altsyncram:altsyncram_component
|-- altsyncram_m9t:auto_generated
|-- altsyncram_t5b2:altsyncram1
|-- sld_mod_ram_rom:mgl_prim2
|-- sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
|-- lpm_counter:ram_rom_addr_reg_rtl_0
|-- cntr_kv8:auto_generated
|-- lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1
|-- cntr_pd8:auto_generated
|-- ADDER10B:u4
|-- REG10B:u5
|-- sin_rom:u6
|-- altsyncram:altsyncram_component
|-- altsyncram_m9t:auto_generated
|-- altsyncram_t5b2:altsyncram1
|-- sld_mod_ram_rom:mgl_prim2
|-- sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
|-- lpm_counter:ram_rom_addr_reg_rtl_0
|-- cntr_kv8:auto_generated
|-- lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1
|-- cntr_pd8:auto_generated
|-- PLL20:u7
|-- altpll:altpll_component
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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