top_7279.fit.eqn

AD0820小程序

--E1_data_7279[4][3] is U7279:inst|FPGA_7279:inst3|data_7279[4][3] at LC_X30_Y12_N7
--operation mode is normal

E1_data_7279[4][3]_lut_out = !E1L98;
E1_data_7279[4][3] = DFFEAS(E1_data_7279[4][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, , , , );


--E1_data_7279[0][3] is U7279:inst|FPGA_7279:inst3|data_7279[0][3] at LC_X29_Y17_N2
--operation mode is normal

E1_data_7279[0][3]_lut_out = !E1L98;
E1_data_7279[0][3] = DFFEAS(E1_data_7279[0][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, , , , );


--E1L178 is U7279:inst|FPGA_7279:inst3|Mux~384 at LC_X29_Y16_N9
--operation mode is normal

E1L178 = E1_seg_cnt[2] & (E1_seg_cnt[1] # E1_data_7279[4][3]) # !E1_seg_cnt[2] & !E1_seg_cnt[1] & (E1_data_7279[0][3]);


--E1_data_7279[6][3] is U7279:inst|FPGA_7279:inst3|data_7279[6][3] at LC_X29_Y17_N4
--operation mode is normal

E1_data_7279[6][3]_lut_out = !E1L98;
E1_data_7279[6][3] = DFFEAS(E1_data_7279[6][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, , , , );


--E1L179 is U7279:inst|FPGA_7279:inst3|Mux~385 at LC_X28_Y16_N2
--operation mode is normal

E1L179 = E1_seg_cnt[1] & (E1L178 & E1_data_7279[6][3] # !E1L178 & (E1_data_7279[2][3])) # !E1_seg_cnt[1] & (E1L178);


--F1_D_BUS[0] is U7279:inst|Display8:inst5|D_BUS[0] at LC_X29_Y16_N6
--operation mode is normal

F1_D_BUS[0]_lut_out = F1_CNT8[1] & F1_CNT8[0] & (C1_Q[28] # !F1_CNT8[2]) # !F1_CNT8[1] & F1_CNT8[2] & (F1_CNT8[0] # C1_Q[28]);
F1_D_BUS[0] = DFFEAS(F1_D_BUS[0]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , F1_state.start, , , , );


--F1_D_BUS[1] is U7279:inst|Display8:inst5|D_BUS[1] at LC_X29_Y16_N0
--operation mode is normal

F1_D_BUS[1]_lut_out = F1_CNT8[0] & F1_CNT8[1] # !F1_CNT8[0] & !F1_CNT8[1] & F1_CNT8[2];
F1_D_BUS[1] = DFFEAS(F1_D_BUS[1]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , F1_state.start, , , , );


--F1_D_BUS[2] is U7279:inst|Display8:inst5|D_BUS[2] at LC_X29_Y16_N4
--operation mode is normal

F1_D_BUS[2]_lut_out = !F1_CNT8[0] & !F1_CNT8[2] & (F1_CNT8[1] # C1_Q[2]);
F1_D_BUS[2] = DFFEAS(F1_D_BUS[2]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , F1_state.start, , , , );


--F1_D_BUS[3] is U7279:inst|Display8:inst5|D_BUS[3] at LC_X29_Y16_N7
--operation mode is normal

F1_D_BUS[3]_lut_out = F1_CNT8[0] & (F1_CNT8[1] $ !F1_CNT8[2]) # !F1_CNT8[0] & !F1_CNT8[1] & F1_CNT8[2] & C1_Q[28];
F1_D_BUS[3] = DFFEAS(F1_D_BUS[3]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , F1_state.start, , , , );


--F1_WR_N is U7279:inst|Display8:inst5|WR_N at LC_X28_Y15_N2
--operation mode is normal

F1_WR_N_lut_out = F1_state.idle & !F1_state.d_hold & (F1_state.d_setup # F1_WR_N);
F1_WR_N = DFFEAS(F1_WR_N_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state1.start_wr is U7279:inst|FPGA_7279:inst3|state1.start_wr at LC_X27_Y15_N4
--operation mode is normal

E1_state1.start_wr_lut_out = F1_WR_N & (E1_state1.start_wr # !E1_state1.idle);
E1_state1.start_wr = DFFEAS(E1_state1.start_wr_lut_out, !GLOBAL(SYS_CLK), VCC, , SYS_RST_N, , , , );


--E1L105 is U7279:inst|FPGA_7279:inst3|Decoder~211 at LC_X29_Y15_N7
--operation mode is normal

E1L105 = F1_WR_N & (E1_state1.start_wr);


--E1L106 is U7279:inst|FPGA_7279:inst3|Decoder~212 at LC_X29_Y15_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_A_BUS[0]_qfbk = F1_A_BUS[0];
E1L106 = E1L105 & F1_A_BUS[2] & F1_A_BUS[0]_qfbk & !F1_A_BUS[1];

--F1_A_BUS[0] is U7279:inst|Display8:inst5|A_BUS[0] at LC_X29_Y15_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_A_BUS[0] = DFFEAS(E1L106, GLOBAL(D3_clk_tmp), VCC, , F1L3, F1_CNT8[0], , , VCC);


--E1L107 is U7279:inst|FPGA_7279:inst3|Decoder~213 at LC_X29_Y15_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_A_BUS[1]_qfbk = F1_A_BUS[1];
E1L107 = E1L105 & F1_A_BUS[0] & F1_A_BUS[1]_qfbk & !F1_A_BUS[2];

--F1_A_BUS[1] is U7279:inst|Display8:inst5|A_BUS[1] at LC_X29_Y15_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_A_BUS[1] = DFFEAS(E1L107, GLOBAL(D3_clk_tmp), VCC, , F1L3, F1_CNT8[1], , , VCC);


--E1L108 is U7279:inst|FPGA_7279:inst3|Decoder~214 at LC_X29_Y15_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_A_BUS[2]_qfbk = F1_A_BUS[2];
E1L108 = E1L105 & F1_A_BUS[0] & !F1_A_BUS[2]_qfbk & !F1_A_BUS[1];

--F1_A_BUS[2] is U7279:inst|Display8:inst5|A_BUS[2] at LC_X29_Y15_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_A_BUS[2] = DFFEAS(E1L108, GLOBAL(D3_clk_tmp), VCC, , F1L3, F1_CNT8[2], , , VCC);


--E1L109 is U7279:inst|FPGA_7279:inst3|Decoder~215 at LC_X29_Y15_N5
--operation mode is normal

E1L109 = E1L105 & F1_A_BUS[0] & F1_A_BUS[2] & F1_A_BUS[1];


--E1L110 is U7279:inst|FPGA_7279:inst3|Decoder~216 at LC_X29_Y15_N9
--operation mode is normal

E1L110 = E1L105 & !F1_A_BUS[0] & !F1_A_BUS[2] & F1_A_BUS[1];


--E1L111 is U7279:inst|FPGA_7279:inst3|Decoder~217 at LC_X29_Y15_N1
--operation mode is normal

E1L111 = E1L105 & !F1_A_BUS[0] & F1_A_BUS[2] & !F1_A_BUS[1];


--E1L112 is U7279:inst|FPGA_7279:inst3|Decoder~218 at LC_X29_Y15_N8
--operation mode is normal

E1L112 = E1L105 & !F1_A_BUS[0] & !F1_A_BUS[2] & !F1_A_BUS[1];


--E1L113 is U7279:inst|FPGA_7279:inst3|Decoder~219 at LC_X29_Y15_N2
--operation mode is normal

E1L113 = E1L105 & !F1_A_BUS[0] & F1_A_BUS[2] & F1_A_BUS[1];


--E1L98 is U7279:inst|FPGA_7279:inst3|decode_bus~1190 at LC_X29_Y16_N1
--operation mode is normal

E1L98 = F1_D_BUS[1] & (F1_D_BUS[2] & F1_D_BUS[0] # !F1_D_BUS[2] & (F1_D_BUS[3])) # !F1_D_BUS[1] & !F1_D_BUS[3] & (F1_D_BUS[0] $ F1_D_BUS[2]);


--F1_CNT8[0] is U7279:inst|Display8:inst5|CNT8[0] at LC_X28_Y15_N4
--operation mode is normal

F1_CNT8[0]_lut_out = F1_CNT8[0] $ F1_state.d_setup;
F1_CNT8[0] = DFFEAS(F1_CNT8[0]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_Q[28] is KEYVALUE:inst1|Q[28] at LC_X23_Y12_N2
--operation mode is normal

C1_Q[28]_lut_out = C1_key_7279[0] # !C1_key_7279[1];
C1_Q[28] = DFFEAS(C1_Q[28]_lut_out, GLOBAL(D3_clk_tmp), VCC, , C1L14, , , , );


--F1_CNT8[2] is U7279:inst|Display8:inst5|CNT8[2] at LC_X28_Y15_N1
--operation mode is normal

F1_CNT8[2]_lut_out = F1_CNT8[2] $ (F1_CNT8[1] & F1_CNT8[0] & F1_state.d_setup);
F1_CNT8[2] = DFFEAS(F1_CNT8[2]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--F1_CNT8[1] is U7279:inst|Display8:inst5|CNT8[1] at LC_X28_Y15_N8
--operation mode is normal

F1_CNT8[1]_lut_out = F1_CNT8[1] $ (F1_CNT8[0] & F1_state.d_setup);
F1_CNT8[1] = DFFEAS(F1_CNT8[1]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--D3_clk_tmp is div:inst2|clk_tmp at LC_X8_Y13_N9
--operation mode is normal

D3_clk_tmp_lut_out = D3_clk_tmp $ (SYS_RST_N & !D3L7);
D3_clk_tmp = DFFEAS(D3_clk_tmp_lut_out, !GLOBAL(SYS_CLK), VCC, , , , , , );


--F1_state.start is U7279:inst|Display8:inst5|state.start at LC_X28_Y15_N5
--operation mode is normal

F1_state.start_lut_out = !F1_state.idle;
F1_state.start = DFFEAS(F1_state.start_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_Q[2] is KEYVALUE:inst1|Q[2] at LC_X23_Y12_N4
--operation mode is normal

C1_Q[2]_lut_out = !C1_key_7279[1] & !C1_key_7279[0];
C1_Q[2] = DFFEAS(C1_Q[2]_lut_out, GLOBAL(D3_clk_tmp), VCC, , C1L14, , , , );


--F1_state.idle is U7279:inst|Display8:inst5|state.idle at LC_X28_Y15_N0
--operation mode is normal

F1_state.idle_lut_out = !F1_state.wr_stop;
F1_state.idle = DFFEAS(F1_state.idle_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--F1L3 is U7279:inst|Display8:inst5|A_BUS[0]~5 at LC_X28_Y15_N7
--operation mode is normal

F1L3 = SYS_RST_N & (!F1_state.idle);


--F1_state.d_hold is U7279:inst|Display8:inst5|state.d_hold at LC_X37_Y13_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_state.d_hold_lut_out = GND;
F1_state.d_hold = DFFEAS(F1_state.d_hold_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , F1_state.d_setup1, , , VCC);


--F1_state.d_setup is U7279:inst|Display8:inst5|state.d_setup at LC_X28_Y15_N6
--operation mode is normal

F1_state.d_setup_lut_out = F1_state.start;
F1_state.d_setup = DFFEAS(F1_state.d_setup_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state1.idle is U7279:inst|FPGA_7279:inst3|state1.idle at LC_X27_Y15_N2
--operation mode is normal

E1_state1.idle_lut_out = !E1_state1.stop & (E1_state1.idle # F1_WR_N);
E1_state1.idle = DFFEAS(E1_state1.idle_lut_out, !GLOBAL(SYS_CLK), VCC, , SYS_RST_N, , , , );


--C1_key_7279[0] is KEYVALUE:inst1|key_7279[0] at LC_X25_Y12_N4
--operation mode is normal

C1_key_7279[0]_lut_out = !E1_key_7279[0];
C1_key_7279[0] = DFFEAS(C1_key_7279[0]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_key_7279[1] is KEYVALUE:inst1|key_7279[1] at LC_X25_Y12_N1
--operation mode is normal

C1_key_7279[1]_lut_out = !E1_key_7279[1];
C1_key_7279[1] = DFFEAS(C1_key_7279[1]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_key_7279[2] is KEYVALUE:inst1|key_7279[2] at LC_X24_Y12_N7
--operation mode is normal

C1_key_7279[2]_lut_out = !E1_key_7279[2];
C1_key_7279[2] = DFFEAS(C1_key_7279[2]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_key_7279[3] is KEYVALUE:inst1|key_7279[3] at LC_X24_Y12_N5
--operation mode is normal

C1_key_7279[3]_lut_out = !E1_key_7279[3];
C1_key_7279[3] = DFFEAS(C1_key_7279[3]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1L12 is KEYVALUE:inst1|Q[2]~102 at LC_X24_Y12_N9
--operation mode is normal

C1L12 = !C1_key_7279[3] # !C1_key_7279[2];


--C1_key_7279[4] is KEYVALUE:inst1|key_7279[4] at LC_X25_Y12_N6
--operation mode is normal

C1_key_7279[4]_lut_out = !E1_key_7279[4];
C1_key_7279[4] = DFFEAS(C1_key_7279[4]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_key_7279[5] is KEYVALUE:inst1|key_7279[5] at LC_X25_Y12_N9
--operation mode is normal

C1_key_7279[5]_lut_out = !E1_key_7279[5];
C1_key_7279[5] = DFFEAS(C1_key_7279[5]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_key_7279[7] is KEYVALUE:inst1|key_7279[7] at LC_X24_Y12_N8
--operation mode is normal

C1_key_7279[7]_lut_out = !E1_key_7279[7];
C1_key_7279[7] = DFFEAS(C1_key_7279[7]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1_key_7279[6] is KEYVALUE:inst1|key_7279[6] at LC_X24_Y12_N0
--operation mode is normal

C1_key_7279[6]_lut_out = !E1_key_7279[6];
C1_key_7279[6] = DFFEAS(C1_key_7279[6]_lut_out, GLOBAL(D3_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C1L13 is KEYVALUE:inst1|Q[2]~103 at LC_X24_Y12_N1
--operation mode is normal

C1L13 = !C1_key_7279[6] # !C1_key_7279[7] # !C1_key_7279[5] # !C1_key_7279[4];


--C1L14 is KEYVALUE:inst1|Q[2]~104 at LC_X24_Y12_N2
--operation mode is normal

C1L14 = !C1L12 & !C1L13 & (!C1_key_7