top_7279.fit.eqn

AD0820小程序

--E1L162 is U7279:inst|FPGA_7279:inst3|Mux~364 at LC_X31_Y15_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][6]_qfbk = E1_data_7279[4][6];
E1L162 = E1_seg_cnt[2] & (E1_seg_cnt[1] # E1_data_7279[4][6]_qfbk) # !E1_seg_cnt[2] & !E1_seg_cnt[1] & (E1_data_7279[0][6]);

--E1_data_7279[4][6] is U7279:inst|FPGA_7279:inst3|data_7279[4][6] at LC_X31_Y15_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][6] = DFFEAS(E1L162, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, E1L102, , , VCC);


--E1_data_7279[6][6] is U7279:inst|FPGA_7279:inst3|data_7279[6][6] at LC_X30_Y14_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[6][6]_lut_out = GND;
E1_data_7279[6][6] = DFFEAS(E1_data_7279[6][6]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, E1L102, , , VCC);


--E1L163 is U7279:inst|FPGA_7279:inst3|Mux~365 at LC_X28_Y16_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][6]_qfbk = E1_data_7279[2][6];
E1L163 = E1L162 & (E1_data_7279[6][6] # !E1_seg_cnt[1]) # !E1L162 & E1_seg_cnt[1] & E1_data_7279[2][6]_qfbk;

--E1_data_7279[2][6] is U7279:inst|FPGA_7279:inst3|data_7279[2][6] at LC_X28_Y16_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][6] = DFFEAS(E1L163, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, E1L102, , , VCC);


--E1_data_7279[1][2] is U7279:inst|FPGA_7279:inst3|data_7279[1][2] at LC_X28_Y16_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[1][2]_lut_out = GND;
E1_data_7279[1][2] = DFFEAS(E1_data_7279[1][2]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, E1L103, , , VCC);


--E1L164 is U7279:inst|FPGA_7279:inst3|Mux~367 at LC_X30_Y16_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][2]_qfbk = E1_data_7279[3][2];
E1L164 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][2]_qfbk) # !E1_seg_cnt[1] & E1_data_7279[1][2]);

--E1_data_7279[3][2] is U7279:inst|FPGA_7279:inst3|data_7279[3][2] at LC_X30_Y16_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][2] = DFFEAS(E1L164, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, E1L103, , , VCC);


--E1L165 is U7279:inst|FPGA_7279:inst3|Mux~368 at LC_X30_Y15_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][2]_qfbk = E1_data_7279[7][2];
E1L165 = E1L164 & (E1_data_7279[7][2]_qfbk # !E1_seg_cnt[2]) # !E1L164 & E1_seg_cnt[2] & (E1_data_7279[5][2]);

--E1_data_7279[7][2] is U7279:inst|FPGA_7279:inst3|data_7279[7][2] at LC_X30_Y15_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][2] = DFFEAS(E1L165, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, E1L103, , , VCC);


--E1_data_7279[0][2] is U7279:inst|FPGA_7279:inst3|data_7279[0][2] at LC_X31_Y15_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[0][2]_lut_out = GND;
E1_data_7279[0][2] = DFFEAS(E1_data_7279[0][2]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, E1L103, , , VCC);


--E1L166 is U7279:inst|FPGA_7279:inst3|Mux~369 at LC_X31_Y15_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][2]_qfbk = E1_data_7279[4][2];
E1L166 = E1_seg_cnt[2] & (E1_seg_cnt[1] # E1_data_7279[4][2]_qfbk) # !E1_seg_cnt[2] & !E1_seg_cnt[1] & (E1_data_7279[0][2]);

--E1_data_7279[4][2] is U7279:inst|FPGA_7279:inst3|data_7279[4][2] at LC_X31_Y15_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][2] = DFFEAS(E1L166, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, E1L103, , , VCC);


--E1_data_7279[6][2] is U7279:inst|FPGA_7279:inst3|data_7279[6][2] at LC_X30_Y14_N4
--operation mode is normal

E1_data_7279[6][2]_lut_out = E1L103;
E1_data_7279[6][2] = DFFEAS(E1_data_7279[6][2]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, , , , );


--E1L167 is U7279:inst|FPGA_7279:inst3|Mux~370 at LC_X30_Y14_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][2]_qfbk = E1_data_7279[2][2];
E1L167 = E1_seg_cnt[1] & (E1L166 & E1_data_7279[6][2] # !E1L166 & (E1_data_7279[2][2]_qfbk)) # !E1_seg_cnt[1] & (E1L166);

--E1_data_7279[2][2] is U7279:inst|FPGA_7279:inst3|data_7279[2][2] at LC_X30_Y14_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][2] = DFFEAS(E1L167, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, E1L103, , , VCC);


--E1_data_7279[1][1] is U7279:inst|FPGA_7279:inst3|data_7279[1][1] at LC_X28_Y16_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[1][1]_lut_out = GND;
E1_data_7279[1][1] = DFFEAS(E1_data_7279[1][1]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, E1L101, , , VCC);


--E1L168 is U7279:inst|FPGA_7279:inst3|Mux~372 at LC_X30_Y16_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][1]_qfbk = E1_data_7279[3][1];
E1L168 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][1]_qfbk) # !E1_seg_cnt[1] & E1_data_7279[1][1]);

--E1_data_7279[3][1] is U7279:inst|FPGA_7279:inst3|data_7279[3][1] at LC_X30_Y16_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][1] = DFFEAS(E1L168, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, E1L101, , , VCC);


--E1L169 is U7279:inst|FPGA_7279:inst3|Mux~373 at LC_X29_Y14_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][1]_qfbk = E1_data_7279[7][1];
E1L169 = E1_seg_cnt[2] & (E1L168 & (E1_data_7279[7][1]_qfbk) # !E1L168 & E1_data_7279[5][1]) # !E1_seg_cnt[2] & (E1L168);

--E1_data_7279[7][1] is U7279:inst|FPGA_7279:inst3|data_7279[7][1] at LC_X29_Y14_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][1] = DFFEAS(E1L169, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, E1L101, , , VCC);


--E1_data_7279[0][1] is U7279:inst|FPGA_7279:inst3|data_7279[0][1] at LC_X29_Y17_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[0][1]_lut_out = GND;
E1_data_7279[0][1] = DFFEAS(E1_data_7279[0][1]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, E1L101, , , VCC);


--E1L170 is U7279:inst|FPGA_7279:inst3|Mux~374 at LC_X30_Y12_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][1]_qfbk = E1_data_7279[4][1];
E1L170 = E1_seg_cnt[1] & E1_seg_cnt[2] # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][1]_qfbk # !E1_seg_cnt[2] & (E1_data_7279[0][1]));

--E1_data_7279[4][1] is U7279:inst|FPGA_7279:inst3|data_7279[4][1] at LC_X30_Y12_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][1] = DFFEAS(E1L170, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, E1L101, , , VCC);


--E1_data_7279[6][1] is U7279:inst|FPGA_7279:inst3|data_7279[6][1] at LC_X30_Y14_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[6][1]_lut_out = GND;
E1_data_7279[6][1] = DFFEAS(E1_data_7279[6][1]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, E1L101, , , VCC);


--E1L171 is U7279:inst|FPGA_7279:inst3|Mux~375 at LC_X30_Y14_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][1]_qfbk = E1_data_7279[2][1];
E1L171 = E1_seg_cnt[1] & (E1L170 & E1_data_7279[6][1] # !E1L170 & (E1_data_7279[2][1]_qfbk)) # !E1_seg_cnt[1] & (E1L170);

--E1_data_7279[2][1] is U7279:inst|FPGA_7279:inst3|data_7279[2][1] at LC_X30_Y14_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][1] = DFFEAS(E1L171, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, E1L101, , , VCC);


--E1_data_7279[1][0] is U7279:inst|FPGA_7279:inst3|data_7279[1][0] at LC_X28_Y16_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[1][0]_lut_out = GND;
E1_data_7279[1][0] = DFFEAS(E1_data_7279[1][0]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, E1L104, , , VCC);


--E1L172 is U7279:inst|FPGA_7279:inst3|Mux~377 at LC_X30_Y15_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][0]_qfbk = E1_data_7279[3][0];
E1L172 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][0]_qfbk) # !E1_seg_cnt[1] & E1_data_7279[1][0]);

--E1_data_7279[3][0] is U7279:inst|FPGA_7279:inst3|data_7279[3][0] at LC_X30_Y15_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][0] = DFFEAS(E1L172, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, E1L104, , , VCC);


--E1L173 is U7279:inst|FPGA_7279:inst3|Mux~378 at LC_X30_Y15_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][0]_qfbk = E1_data_7279[7][0];
E1L173 = E1L172 & (E1_data_7279[7][0]_qfbk # !E1_seg_cnt[2]) # !E1L172 & E1_seg_cnt[2] & (E1_data_7279[5][0]);

--E1_data_7279[7][0] is U7279:inst|FPGA_7279:inst3|data_7279[7][0] at LC_X30_Y15_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][0] = DFFEAS(E1L173, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, E1L104, , , VCC);


--E1_data_7279[0][0] is U7279:inst|FPGA_7279:inst3|data_7279[0][0] at LC_X31_Y15_N3
--operation mode is normal

E1_data_7279[0][0]_lut_out = E1L104;
E1_data_7279[0][0] = DFFEAS(E1_data_7279[0][0]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, , , , );


--E1L174 is U7279:inst|FPGA_7279:inst3|Mux~379 at LC_X31_Y15_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][0]_qfbk = E1_data_7279[4][0];
E1L174 = E1_seg_cnt[2] & (E1_seg_cnt[1] # E1_data_7279[4][0]_qfbk) # !E1_seg_cnt[2] & !E1_seg_cnt[1] & (E1_data_7279[0][0]);

--E1_data_7279[4][0] is U7279:inst|FPGA_7279:inst3|data_7279[4][0] at LC_X31_Y15_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][0] = DFFEAS(E1L174, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, E1L104, , , VCC);


--E1_data_7279[6][0] is U7279:inst|FPGA_7279:inst3|data_7279[6][0] at LC_X30_Y14_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[6][0]_lut_out = GND;
E1_data_7279[6][0] = DFFEAS(E1_data_7279[6][0]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, E1L104, , , VCC);


--E1L175 is U7279:inst|FPGA_7279:inst3|Mux~380 at LC_X30_Y14_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][0]_qfbk = E1_data_7279[2][0];
E1L175 = E1_seg_cnt[1] & (E1L174 & (E1_data_7279[6][0]) # !E1L174 & E1_data_7279[2][0]_qfbk) # !E1_seg_cnt[1] & E1L174;

--E1_data_7279[2][0] is U7279:inst|FPGA_7279:inst3|data_7279[2][0] at LC_X30_Y14_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][0] = DFFEAS(E1L175, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, E1L104, , , VCC);


--E1_data_7279[5][3] is U7279:inst|FPGA_7279:inst3|data_7279[5][3] at LC_X29_Y16_N3
--operation mode is normal

E1_data_7279[5][3]_lut_out = !E1L98;
E1_data_7279[5][3] = DFFEAS(E1_data_7279[5][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L106, , , , );


--E1_data_7279[3][3] is U7279:inst|FPGA_7279:inst3|data_7279[3][3] at LC_X30_Y15_N6
--operation mode is normal

E1_data_7279[3][3]_lut_out = !E1L98;
E1_data_7279[3][3] = DFFEAS(E1_data_7279[3][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, , , , );


--E1_data_7279[1][3] is U7279:inst|FPGA_7279:inst3|data_7279[1][3] at LC_X28_Y16_N3
--operation mode is normal

E1_data_7279[1][3]_lut_out = !E1L98;
E1_data_7279[1][3] = DFFEAS(E1_data_7279[1][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, , , , );


--E1L176 is U7279:inst|FPGA_7279:inst3|Mux~382 at LC_X29_Y16_N2
--operation mode is normal

E1L176 = E1_seg_cnt[2] & E1_seg_cnt[1] # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][3]) # !E1_seg_cnt[1] & E1_data_7279[1][3]);


--E1_data_7279[7][3] is U7279:inst|FPGA_7279:inst3|data_7279[7][3] at LC_X30_Y15_N7
--operation mode is normal

E1_data_7279[7][3]_lut_out = !E1L98;
E1_data_7279[7][3] = DFFEAS(E1_data_7279[7][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, , , , );


--E1L177 is U7279:inst|FPGA_7279:inst3|Mux~383 at LC_X29_Y16_N5
--operation mode is normal

E1L177 = E1_seg_cnt[2] & (E1L176 & E1_data_7279[7][3] # !E1L176 & (E1_data_7279[5][3])) # !E1_seg_cnt[2] & (E1L176);


--E1_data_7279[2][3] is U7279:inst|FPGA_7279:inst3|data_7279[2][3] at LC_X28_Y16_N7
--operation mode is normal

E1_data_7279[2][3]_lut_out = !E1L98;
E1_data_7279[2][3] = DFFEAS(E1_data_7279[2][3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, , , , );