top_7279.fit.eqn

AD0820小程序

--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[2]_qfbk = E1_data_tmp1[2];
E1L151 = E1L150 & (E1_data_tmp1[3] # !E1_sdata_cnt[1]) # !E1L150 & E1_sdata_cnt[1] & E1_data_tmp1[2]_qfbk;

--E1_data_tmp1[2] is U7279:inst|FPGA_7279:inst3|data_tmp1[2] at LC_X29_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[2] = DFFEAS(E1L151, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_tmp[2], , , VCC);


--E1L210 is U7279:inst|FPGA_7279:inst3|Select~1562 at LC_X29_Y13_N3
--operation mode is normal

E1L210 = E1_state.shift_data_low & (E1_sdata_cnt[2] & E1L209 # !E1_sdata_cnt[2] & (E1L151));


--E1L211 is U7279:inst|FPGA_7279:inst3|Select~1563 at LC_X29_Y10_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[7]_qfbk = E1_cmd_tmp1[7];
E1L211 = E1_scmd_cnt[2] & (E1_scmd_cnt[1] & E1_scmd_cnt[0] & E1_cmd_tmp1[7]_qfbk # !E1_scmd_cnt[1] & !E1_scmd_cnt[0]);

--E1_cmd_tmp1[7] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[7] at LC_X29_Y10_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[7] = DFFEAS(E1L211, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_cmd_tmp[7], , , VCC);


--E1L212 is U7279:inst|FPGA_7279:inst3|Select~1564 at LC_X29_Y10_N2
--operation mode is normal

E1L212 = !E1_scmd_cnt[2] & !E1_scmd_cnt[0] & E1_scmd_cnt[1] & E1_cmd_tmp1[2];


--E1L213 is U7279:inst|FPGA_7279:inst3|Select~1565 at LC_X29_Y10_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[1]_qfbk = E1_cmd_tmp1[1];
E1L213 = !E1_scmd_cnt[2] & (E1_scmd_cnt[0] & E1_cmd_tmp1[1]_qfbk # !E1_scmd_cnt[0] & (E1_cmd_tmp1[0]));

--E1_cmd_tmp1[1] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[1] at LC_X29_Y10_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[1] = DFFEAS(E1L213, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_cmd_tmp[1], , , VCC);


--E1L214 is U7279:inst|FPGA_7279:inst3|Select~1566 at LC_X29_Y10_N1
--operation mode is normal

E1L214 = E1L212 # E1L211 # E1L213 & !E1_scmd_cnt[1];


--E1L215 is U7279:inst|FPGA_7279:inst3|Select~1568 at LC_X30_Y12_N2
--operation mode is normal

E1L215 = E1_state.idle & !E1L199 # !E1_state.idle & (!KEY7279);


--E1L198 is U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 at LC_X30_Y12_N6
--operation mode is normal

E1L198 = SYS_RST_N & !E1_state.idle & (KEY7279);


--E1_data_tmp[5] is U7279:inst|FPGA_7279:inst3|data_tmp[5] at LC_X29_Y14_N7
--operation mode is normal

E1_data_tmp[5]_lut_out = E1_seg_cnt[0] & E1L153 # !E1_seg_cnt[0] & (E1L155);
E1_data_tmp[5] = DFFEAS(E1_data_tmp[5]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_tmp[4] is U7279:inst|FPGA_7279:inst3|data_tmp[4] at LC_X29_Y14_N4
--operation mode is normal

E1_data_tmp[4]_lut_out = E1_seg_cnt[0] & E1L157 # !E1_seg_cnt[0] & (E1L159);
E1_data_tmp[4] = DFFEAS(E1_data_tmp[4]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_tmp[6] is U7279:inst|FPGA_7279:inst3|data_tmp[6] at LC_X29_Y14_N8
--operation mode is normal

E1_data_tmp[6]_lut_out = E1_seg_cnt[0] & E1L161 # !E1_seg_cnt[0] & (E1L163);
E1_data_tmp[6] = DFFEAS(E1_data_tmp[6]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_tmp[2] is U7279:inst|FPGA_7279:inst3|data_tmp[2] at LC_X29_Y14_N0
--operation mode is normal

E1_data_tmp[2]_lut_out = E1_seg_cnt[0] & E1L165 # !E1_seg_cnt[0] & (E1L167);
E1_data_tmp[2] = DFFEAS(E1_data_tmp[2]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_tmp[1] is U7279:inst|FPGA_7279:inst3|data_tmp[1] at LC_X29_Y14_N5
--operation mode is normal

E1_data_tmp[1]_lut_out = E1_seg_cnt[0] & (E1L169) # !E1_seg_cnt[0] & (E1L171);
E1_data_tmp[1] = DFFEAS(E1_data_tmp[1]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_tmp[0] is U7279:inst|FPGA_7279:inst3|data_tmp[0] at LC_X29_Y14_N2
--operation mode is normal

E1_data_tmp[0]_lut_out = E1_seg_cnt[0] & (E1L173) # !E1_seg_cnt[0] & E1L175;
E1_data_tmp[0] = DFFEAS(E1_data_tmp[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_tmp[3] is U7279:inst|FPGA_7279:inst3|data_tmp[3] at LC_X29_Y14_N3
--operation mode is normal

E1_data_tmp[3]_lut_out = E1_seg_cnt[0] & E1L177 # !E1_seg_cnt[0] & (E1L179);
E1_data_tmp[3] = DFFEAS(E1_data_tmp[3]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_data_7279[1][5] is U7279:inst|FPGA_7279:inst3|data_7279[1][5] at LC_X29_Y15_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[1][5]_lut_out = GND;
E1_data_7279[1][5] = DFFEAS(E1_data_7279[1][5]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, E1L99, , , VCC);


--E1L152 is U7279:inst|FPGA_7279:inst3|Mux~352 at LC_X30_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][5]_qfbk = E1_data_7279[3][5];
E1L152 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][5]_qfbk) # !E1_seg_cnt[1] & E1_data_7279[1][5]);

--E1_data_7279[3][5] is U7279:inst|FPGA_7279:inst3|data_7279[3][5] at LC_X30_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][5] = DFFEAS(E1L152, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, E1L99, , , VCC);


--E1L153 is U7279:inst|FPGA_7279:inst3|Mux~353 at LC_X30_Y15_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][5]_qfbk = E1_data_7279[7][5];
E1L153 = E1L152 & (E1_data_7279[7][5]_qfbk # !E1_seg_cnt[2]) # !E1L152 & E1_seg_cnt[2] & (E1_data_7279[5][5]);

--E1_data_7279[7][5] is U7279:inst|FPGA_7279:inst3|data_7279[7][5] at LC_X30_Y15_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][5] = DFFEAS(E1L153, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, E1L99, , , VCC);


--E1_data_7279[0][5] is U7279:inst|FPGA_7279:inst3|data_7279[0][5] at LC_X31_Y15_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[0][5]_lut_out = GND;
E1_data_7279[0][5] = DFFEAS(E1_data_7279[0][5]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, E1L99, , , VCC);


--E1L154 is U7279:inst|FPGA_7279:inst3|Mux~354 at LC_X31_Y15_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][5]_qfbk = E1_data_7279[4][5];
E1L154 = E1_seg_cnt[2] & (E1_seg_cnt[1] # E1_data_7279[4][5]_qfbk) # !E1_seg_cnt[2] & !E1_seg_cnt[1] & (E1_data_7279[0][5]);

--E1_data_7279[4][5] is U7279:inst|FPGA_7279:inst3|data_7279[4][5] at LC_X31_Y15_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][5] = DFFEAS(E1L154, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, E1L99, , , VCC);


--E1_data_7279[6][5] is U7279:inst|FPGA_7279:inst3|data_7279[6][5] at LC_X30_Y14_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[6][5]_lut_out = GND;
E1_data_7279[6][5] = DFFEAS(E1_data_7279[6][5]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, E1L99, , , VCC);


--E1L155 is U7279:inst|FPGA_7279:inst3|Mux~355 at LC_X30_Y14_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][5]_qfbk = E1_data_7279[2][5];
E1L155 = E1_seg_cnt[1] & (E1L154 & (E1_data_7279[6][5]) # !E1L154 & E1_data_7279[2][5]_qfbk) # !E1_seg_cnt[1] & E1L154;

--E1_data_7279[2][5] is U7279:inst|FPGA_7279:inst3|data_7279[2][5] at LC_X30_Y14_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][5] = DFFEAS(E1L155, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, E1L99, , , VCC);


--E1_data_7279[1][4] is U7279:inst|FPGA_7279:inst3|data_7279[1][4] at LC_X28_Y16_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[1][4]_lut_out = GND;
E1_data_7279[1][4] = DFFEAS(E1_data_7279[1][4]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, E1L100, , , VCC);


--E1L156 is U7279:inst|FPGA_7279:inst3|Mux~357 at LC_X30_Y16_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][4]_qfbk = E1_data_7279[3][4];
E1L156 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][4]_qfbk) # !E1_seg_cnt[1] & E1_data_7279[1][4]);

--E1_data_7279[3][4] is U7279:inst|FPGA_7279:inst3|data_7279[3][4] at LC_X30_Y16_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][4] = DFFEAS(E1L156, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, E1L100, , , VCC);


--E1L157 is U7279:inst|FPGA_7279:inst3|Mux~358 at LC_X30_Y15_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][4]_qfbk = E1_data_7279[7][4];
E1L157 = E1_seg_cnt[2] & (E1L156 & (E1_data_7279[7][4]_qfbk) # !E1L156 & E1_data_7279[5][4]) # !E1_seg_cnt[2] & (E1L156);

--E1_data_7279[7][4] is U7279:inst|FPGA_7279:inst3|data_7279[7][4] at LC_X30_Y15_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][4] = DFFEAS(E1L157, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, E1L100, , , VCC);


--E1_data_7279[0][4] is U7279:inst|FPGA_7279:inst3|data_7279[0][4] at LC_X31_Y15_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[0][4]_lut_out = GND;
E1_data_7279[0][4] = DFFEAS(E1_data_7279[0][4]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, E1L100, , , VCC);


--E1L158 is U7279:inst|FPGA_7279:inst3|Mux~359 at LC_X31_Y15_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][4]_qfbk = E1_data_7279[4][4];
E1L158 = E1_seg_cnt[2] & (E1_seg_cnt[1] # E1_data_7279[4][4]_qfbk) # !E1_seg_cnt[2] & !E1_seg_cnt[1] & (E1_data_7279[0][4]);

--E1_data_7279[4][4] is U7279:inst|FPGA_7279:inst3|data_7279[4][4] at LC_X31_Y15_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[4][4] = DFFEAS(E1L158, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L111, E1L100, , , VCC);


--E1_data_7279[6][4] is U7279:inst|FPGA_7279:inst3|data_7279[6][4] at LC_X30_Y14_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[6][4]_lut_out = GND;
E1_data_7279[6][4] = DFFEAS(E1_data_7279[6][4]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L113, E1L100, , , VCC);


--E1L159 is U7279:inst|FPGA_7279:inst3|Mux~360 at LC_X28_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][4]_qfbk = E1_data_7279[2][4];
E1L159 = E1L158 & (E1_data_7279[6][4] # !E1_seg_cnt[1]) # !E1L158 & E1_seg_cnt[1] & E1_data_7279[2][4]_qfbk;

--E1_data_7279[2][4] is U7279:inst|FPGA_7279:inst3|data_7279[2][4] at LC_X28_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[2][4] = DFFEAS(E1L159, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L110, E1L100, , , VCC);


--E1_data_7279[1][6] is U7279:inst|FPGA_7279:inst3|data_7279[1][6] at LC_X28_Y16_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[1][6]_lut_out = GND;
E1_data_7279[1][6] = DFFEAS(E1_data_7279[1][6]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L108, E1L102, , , VCC);


--E1L160 is U7279:inst|FPGA_7279:inst3|Mux~362 at LC_X30_Y16_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][6]_qfbk = E1_data_7279[3][6];
E1L160 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & (E1_data_7279[3][6]_qfbk) # !E1_seg_cnt[1] & E1_data_7279[1][6]);

--E1_data_7279[3][6] is U7279:inst|FPGA_7279:inst3|data_7279[3][6] at LC_X30_Y16_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[3][6] = DFFEAS(E1L160, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L107, E1L102, , , VCC);


--E1L161 is U7279:inst|FPGA_7279:inst3|Mux~363 at LC_X30_Y15_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][6]_qfbk = E1_data_7279[7][6];
E1L161 = E1L160 & (E1_data_7279[7][6]_qfbk # !E1_seg_cnt[2]) # !E1L160 & E1_seg_cnt[2] & (E1_data_7279[5][6]);

--E1_data_7279[7][6] is U7279:inst|FPGA_7279:inst3|data_7279[7][6] at LC_X30_Y15_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[7][6] = DFFEAS(E1L161, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L109, E1L102, , , VCC);


--E1_data_7279[0][6] is U7279:inst|FPGA_7279:inst3|data_7279[0][6] at LC_X31_Y15_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_7279[0][6]_lut_out = GND;
E1_data_7279[0][6] = DFFEAS(E1_data_7279[0][6]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , E1L112, E1L102, , , VCC);