top_7279.fit.eqn

AD0820小程序

D2L24_cout_1 = D2_fre_N[6] & (!D2L21);
D2L24 = CARRY(D2L24_cout_1);


--D2L30 is U7279:inst|div:inst1|LessThan~119 at LC_X41_Y16_N2
--operation mode is normal

D2L30 = !D2_fre_N[4] & !D2_fre_N[5] & !D2_fre_N[6];


--D2_fre_N[7] is U7279:inst|div:inst1|fre_N[7] at LC_X40_Y16_N7
--operation mode is arithmetic

D2_fre_N[7]_carry_eqn = (!D2L16 & D2L23) # (D2L16 & D2L24);
D2_fre_N[7]_lut_out = D2_fre_N[7] $ (D2_fre_N[7]_carry_eqn);
D2_fre_N[7] = DFFEAS(D2_fre_N[7]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L26 is U7279:inst|div:inst1|fre_N[7]~172 at LC_X40_Y16_N7
--operation mode is arithmetic

D2L26_cout_0 = !D2L23 # !D2_fre_N[7];
D2L26 = CARRY(D2L26_cout_0);

--D2L27 is U7279:inst|div:inst1|fre_N[7]~172COUT1_185 at LC_X40_Y16_N7
--operation mode is arithmetic

D2L27_cout_1 = !D2L24 # !D2_fre_N[7];
D2L27 = CARRY(D2L27_cout_1);


--D2_fre_N[8] is U7279:inst|div:inst1|fre_N[8] at LC_X40_Y16_N8
--operation mode is normal

D2_fre_N[8]_carry_eqn = (!D2L16 & D2L26) # (D2L16 & D2L27);
D2_fre_N[8]_lut_out = D2_fre_N[8] $ !D2_fre_N[8]_carry_eqn;
D2_fre_N[8] = DFFEAS(D2_fre_N[8]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );


--D2L31 is U7279:inst|div:inst1|LessThan~120 at LC_X40_Y16_N9
--operation mode is normal

D2L31 = D2_fre_N[7] & D2_fre_N[8] & (!D2L29 # !D2L30);


--E1_delay_cnt[1] is U7279:inst|FPGA_7279:inst3|delay_cnt[1] at LC_X30_Y10_N4
--operation mode is normal

E1_delay_cnt[1]_lut_out = E1L128 & (E1_delay_cnt[0] $ !E1_delay_cnt[1] # !E1L183) # !E1L128 & (E1_delay_cnt[1]);
E1_delay_cnt[1] = DFFEAS(E1_delay_cnt[1]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , , , , , );


--E1L203 is U7279:inst|FPGA_7279:inst3|Select~1549 at LC_X28_Y10_N9
--operation mode is normal

E1L203 = !E1_delay_cnt[1] & (E1_state.start_delay);


--E1L149 is U7279:inst|FPGA_7279:inst3|LessThan~112 at LC_X30_Y10_N0
--operation mode is normal

E1L149 = E1_scmd_cnt[1] # E1_scmd_cnt[0];


--E1L204 is U7279:inst|FPGA_7279:inst3|Select~1550 at LC_X30_Y12_N3
--operation mode is normal

E1L204 = E1L203 # E1_state.shift_cmd_high & (E1_scmd_cnt[2] # E1L149);

--E1_state.shift_cmd_low is U7279:inst|FPGA_7279:inst3|state.shift_cmd_low at LC_X30_Y12_N3
--operation mode is normal

E1_state.shift_cmd_low = DFFEAS(E1L204, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1L205 is U7279:inst|FPGA_7279:inst3|Select~1551 at LC_X28_Y12_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.shift_data_high_qfbk = E1_state.shift_data_high;
E1L205 = E1_state.shift_data_high_qfbk & (E1_sdata_cnt[2] # E1_sdata_cnt[1] # E1_sdata_cnt[0]);

--E1_state.shift_data_high is U7279:inst|FPGA_7279:inst3|state.shift_data_high at LC_X28_Y12_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.shift_data_high = DFFEAS(E1L205, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , E1_state.shift_data_low, , , VCC);


--E1L206 is U7279:inst|FPGA_7279:inst3|Select~1552 at LC_X28_Y10_N8
--operation mode is normal

E1L206 = !E1_delay_cnt[1] & (E1_state.next_delay);


--E1_cmd_tmp[2] is U7279:inst|FPGA_7279:inst3|cmd_tmp[2] at LC_X29_Y11_N2
--operation mode is normal

E1_cmd_tmp[2]_lut_out = E1_seg_cnt[2] # !KEY7279;
E1_cmd_tmp[2] = DFFEAS(E1_cmd_tmp[2]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L12, , , , );


--E1_cmd_tmp[0] is U7279:inst|FPGA_7279:inst3|cmd_tmp[0] at LC_X29_Y11_N5
--operation mode is normal

E1_cmd_tmp[0]_lut_out = E1_seg_cnt[0] # !KEY7279;
E1_cmd_tmp[0] = DFFEAS(E1_cmd_tmp[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L12, , , , );


--E1_cmd_tmp[1] is U7279:inst|FPGA_7279:inst3|cmd_tmp[1] at LC_X29_Y11_N7
--operation mode is normal

E1_cmd_tmp[1]_lut_out = KEY7279 & (E1_seg_cnt[1]);
E1_cmd_tmp[1] = DFFEAS(E1_cmd_tmp[1]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L12, , , , );


--A1L7 is rtl~189 at LC_X29_Y11_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp[7]_qfbk = E1_cmd_tmp[7];
A1L7 = E1_cmd_tmp[2] & !E1_cmd_tmp[1] & !E1_cmd_tmp[7]_qfbk & E1_cmd_tmp[0];

--E1_cmd_tmp[7] is U7279:inst|FPGA_7279:inst3|cmd_tmp[7] at LC_X29_Y11_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp[7] = DFFEAS(A1L7, !GLOBAL(D2_clk_tmp), VCC, , E1L12, KEY7279, , , VCC);


--E1L207 is U7279:inst|FPGA_7279:inst3|Select~1553 at LC_X28_Y10_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.shift_key_high1_qfbk = E1_state.shift_key_high1;
E1L207 = E1_state.shift_key_high1_qfbk & (E1_sdata_cnt[2] # E1_sdata_cnt[0] # E1_sdata_cnt[1]);

--E1_state.shift_key_high1 is U7279:inst|FPGA_7279:inst3|state.shift_key_high1 at LC_X28_Y10_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.shift_key_high1 = DFFEAS(E1L207, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , E1_state.shift_key_high, , , VCC);


--E1L14Q is U7279:inst|FPGA_7279:inst3|DAT7279~reg0 at LC_X29_Y13_N4
--operation mode is normal

E1L14Q_lut_out = E1L210 # E1L214 & !E1_state.shift_data_low;
E1L14Q = DFFEAS(E1L14Q_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , E1L215, , , , );


--E1L181Q is U7279:inst|FPGA_7279:inst3|process0~1 at LC_X29_Y12_N6
--operation mode is normal

E1L181Q_lut_out = !E1_state.shift_key_low & (E1_state.idle);
E1L181Q = DFFEAS(E1L181Q_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , E1L215, , , , );


--E1L193 is U7279:inst|FPGA_7279:inst3|sdata_cnt[2]~426 at LC_X28_Y10_N7
--operation mode is normal

E1L193 = SYS_RST_N & (E1L207 # E1L206 # E1L205);


--E1L188 is U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 at LC_X30_Y10_N6
--operation mode is normal

E1L188 = E1L204 & (SYS_RST_N);


--E1_data_start is U7279:inst|FPGA_7279:inst3|data_start at LC_X29_Y11_N9
--operation mode is normal

E1_data_start_lut_out = E1_state.idle & (E1_data_start) # !E1_state.idle & KEY7279;
E1_data_start = DFFEAS(E1_data_start_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1L84 is U7279:inst|FPGA_7279:inst3|data_tmp1[0]~7 at LC_X28_Y10_N2
--operation mode is normal

E1L84 = SYS_RST_N & (E1_state.start);


--E1_delay_cnt[0] is U7279:inst|FPGA_7279:inst3|delay_cnt[0] at LC_X30_Y10_N1
--operation mode is normal

E1_delay_cnt[0]_lut_out = E1L128 & (E1_state.shift_cmd_high # E1_state.start # !E1_delay_cnt[0]) # !E1L128 & (E1_delay_cnt[0]);
E1_delay_cnt[0] = DFFEAS(E1_delay_cnt[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , , , , , );


--E1L182 is U7279:inst|FPGA_7279:inst3|reduce_or~52 at LC_X28_Y10_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.shift_cmd_high_qfbk = E1_state.shift_cmd_high;
E1L182 = E1_state.start # E1_state.start_delay # E1_state.shift_cmd_high_qfbk # E1_state.next_delay;

--E1_state.shift_cmd_high is U7279:inst|FPGA_7279:inst3|state.shift_cmd_high at LC_X28_Y10_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_state.shift_cmd_high = DFFEAS(E1L182, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , E1_state.shift_cmd_low, , , VCC);


--E1L126 is U7279:inst|FPGA_7279:inst3|delay_cnt[1]~779 at LC_X30_Y10_N9
--operation mode is normal

E1L126 = !E1L206 & !E1L203 & SYS_RST_N & E1L182;


--E1L127 is U7279:inst|FPGA_7279:inst3|delay_cnt[1]~780 at LC_X30_Y10_N2
--operation mode is normal

E1L127 = !E1_scmd_cnt[1] & (!E1_scmd_cnt[2] & !E1_scmd_cnt[0]);


--E1L128 is U7279:inst|FPGA_7279:inst3|delay_cnt[1]~781 at LC_X30_Y10_N3
--operation mode is normal

E1L128 = E1L126 & (E1L180 & E1L127 # !E1_state.shift_cmd_high);


--E1L183 is U7279:inst|FPGA_7279:inst3|reduce_or~53 at LC_X29_Y11_N4
--operation mode is normal

E1L183 = !E1_state.shift_cmd_high & !E1_state.start;


--E1_seg_cnt[2] is U7279:inst|FPGA_7279:inst3|seg_cnt[2] at LC_X30_Y12_N5
--operation mode is normal

E1_seg_cnt[2]_lut_out = E1_seg_cnt[2] $ (E1_seg_cnt[1] & E1_seg_cnt[0] & E1L198);
E1_seg_cnt[2] = DFFEAS(E1_seg_cnt[2]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , , , , , );


--E1L12 is U7279:inst|FPGA_7279:inst3|cmd_tmp[7]~46 at LC_X30_Y12_N4
--operation mode is normal

E1L12 = SYS_RST_N & (!E1_state.idle);


--E1_seg_cnt[0] is U7279:inst|FPGA_7279:inst3|seg_cnt[0] at LC_X29_Y14_N9
--operation mode is normal

E1_seg_cnt[0]_lut_out = !E1_seg_cnt[0];
E1_seg_cnt[0] = DFFEAS(E1_seg_cnt[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L198, , , , );


--E1_seg_cnt[1] is U7279:inst|FPGA_7279:inst3|seg_cnt[1] at LC_X30_Y12_N9
--operation mode is normal

E1_seg_cnt[1]_lut_out = E1_seg_cnt[1] $ (E1_seg_cnt[0] & E1L198);
E1_seg_cnt[1] = DFFEAS(E1_seg_cnt[1]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , , , , , );


--E1_data_tmp1[4] is U7279:inst|FPGA_7279:inst3|data_tmp1[4] at LC_X29_Y13_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[4]_lut_out = GND;
E1_data_tmp1[4] = DFFEAS(E1_data_tmp1[4]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_tmp[4], , , VCC);


--E1L208 is U7279:inst|FPGA_7279:inst3|Select~1560 at LC_X29_Y13_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[5]_qfbk = E1_data_tmp1[5];
E1L208 = E1_sdata_cnt[0] & E1_data_tmp1[5]_qfbk # !E1_sdata_cnt[0] & (E1_data_tmp1[4]);

--E1_data_tmp1[5] is U7279:inst|FPGA_7279:inst3|data_tmp1[5] at LC_X29_Y13_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[5] = DFFEAS(E1L208, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_tmp[5], , , VCC);


--E1L209 is U7279:inst|FPGA_7279:inst3|Select~1561 at LC_X29_Y13_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[6]_qfbk = E1_data_tmp1[6];
E1L209 = E1_sdata_cnt[1] & (E1_data_tmp1[6]_qfbk & !E1_sdata_cnt[0]) # !E1_sdata_cnt[1] & E1L208;

--E1_data_tmp1[6] is U7279:inst|FPGA_7279:inst3|data_tmp1[6] at LC_X29_Y13_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[6] = DFFEAS(E1L209, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_tmp[6], , , VCC);


--E1_data_tmp1[0] is U7279:inst|FPGA_7279:inst3|data_tmp1[0] at LC_X29_Y13_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[0]_lut_out = GND;
E1_data_tmp1[0] = DFFEAS(E1_data_tmp1[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_tmp[0], , , VCC);


--E1L150 is U7279:inst|FPGA_7279:inst3|Mux~350 at LC_X29_Y13_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[1]_qfbk = E1_data_tmp1[1];
E1L150 = E1_sdata_cnt[1] & (E1_sdata_cnt[0]) # !E1_sdata_cnt[1] & (E1_sdata_cnt[0] & (E1_data_tmp1[1]_qfbk) # !E1_sdata_cnt[0] & E1_data_tmp1[0]);

--E1_data_tmp1[1] is U7279:inst|FPGA_7279:inst3|data_tmp1[1] at LC_X29_Y13_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_tmp1[1] = DFFEAS(E1L150, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_tmp[1], , , VCC);


--E1_data_tmp1[3] is U7279:inst|FPGA_7279:inst3|data_tmp1[3] at LC_X29_Y13_N0
--operation mode is normal

E1_data_tmp1[3]_lut_out = E1_data_tmp[3];
E1_data_tmp1[3] = DFFEAS(E1_data_tmp1[3]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L84, , , , );


--E1L151 is U7279:inst|FPGA_7279:inst3|Mux~351 at LC_X29_Y13_N2
--operation mode is normal