top_7279.fit.eqn

AD0820小程序

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--E1_CS7279 is U7279:inst|FPGA_7279:inst3|CS7279 at LC_X29_Y11_N3
--operation mode is normal

E1_CS7279_lut_out = !E1_state.finish & (E1_CS7279 # E1_state.start);
E1_CS7279 = DFFEAS(E1_CS7279_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_CLK7279 is U7279:inst|FPGA_7279:inst3|CLK7279 at LC_X29_Y11_N1
--operation mode is normal

E1_CLK7279_lut_out = E1_CLK7279 & (E1_state.shift_key_high # !E1L200) # !E1L199;
E1_CLK7279 = DFFEAS(E1_CLK7279_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state.finish is U7279:inst|FPGA_7279:inst3|state.finish at LC_X29_Y10_N5
--operation mode is normal

E1_state.finish_lut_out = E1L201 # E1L202 & !E1L180;
E1_state.finish = DFFEAS(E1_state.finish_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state.start is U7279:inst|FPGA_7279:inst3|state.start at LC_X28_Y10_N3
--operation mode is normal

E1_state.start_lut_out = !E1_state.idle;
E1_state.start = DFFEAS(E1_state.start_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--D2_clk_tmp is U7279:inst|div:inst1|clk_tmp at LC_X15_Y13_N2
--operation mode is normal

D2_clk_tmp_lut_out = D2_clk_tmp $ (SYS_RST_N & D2L31);
D2_clk_tmp = DFFEAS(D2_clk_tmp_lut_out, !GLOBAL(SYS_CLK), VCC, , , , , , );


--E1_state.shift_data_low is U7279:inst|FPGA_7279:inst3|state.shift_data_low at LC_X28_Y12_N9
--operation mode is normal

E1_state.shift_data_low_lut_out = E1L205 # E1_state.next_delay & !A1L7 & !E1_delay_cnt[1];
E1_state.shift_data_low = DFFEAS(E1_state.shift_data_low_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state.shift_key_low is U7279:inst|FPGA_7279:inst3|state.shift_key_low at LC_X29_Y12_N7
--operation mode is normal

E1_state.shift_key_low_lut_out = E1L207 # !E1_delay_cnt[1] & A1L7 & E1_state.next_delay;
E1_state.shift_key_low = DFFEAS(E1_state.shift_key_low_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1L199 is U7279:inst|FPGA_7279:inst3|Select~1543 at LC_X30_Y12_N8
--operation mode is normal

E1L199 = !E1_state.shift_cmd_low & !E1_state.shift_data_low & !E1_state.shift_key_low;


--E1_state.next_delay is U7279:inst|FPGA_7279:inst3|state.next_delay at LC_X28_Y10_N5
--operation mode is normal

E1_state.next_delay_lut_out = E1_state.next_delay & (E1_delay_cnt[1] # E1L180 & E1L202) # !E1_state.next_delay & E1L180 & (E1L202);
E1_state.next_delay = DFFEAS(E1_state.next_delay_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state.start_delay is U7279:inst|FPGA_7279:inst3|state.start_delay at LC_X28_Y10_N1
--operation mode is normal

E1_state.start_delay_lut_out = E1_state.start # E1_delay_cnt[1] & E1_state.start_delay;
E1_state.start_delay = DFFEAS(E1_state.start_delay_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1_state.idle is U7279:inst|FPGA_7279:inst3|state.idle at LC_X30_Y12_N0
--operation mode is normal

E1_state.idle_lut_out = !E1_state.finish;
E1_state.idle = DFFEAS(E1_state.idle_lut_out, !GLOBAL(D2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--E1L200 is U7279:inst|FPGA_7279:inst3|Select~1544 at LC_X29_Y11_N8
--operation mode is normal

E1L200 = E1_state.idle & !E1_state.start_delay & !E1_state.finish & !E1_state.next_delay;


--E1_sdata_cnt[2] is U7279:inst|FPGA_7279:inst3|sdata_cnt[2] at LC_X28_Y12_N7
--operation mode is normal

E1_sdata_cnt[2]_lut_out = E1L193 & (E1_state.next_delay # E1_sdata_cnt[2] $ !E1L148) # !E1L193 & E1_sdata_cnt[2];
E1_sdata_cnt[2] = DFFEAS(E1_sdata_cnt[2]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , , , , , );


--E1_sdata_cnt[1] is U7279:inst|FPGA_7279:inst3|sdata_cnt[1] at LC_X28_Y10_N6
--operation mode is normal

E1_sdata_cnt[1]_lut_out = E1_state.next_delay # E1_sdata_cnt[1] $ !E1_sdata_cnt[0];
E1_sdata_cnt[1] = DFFEAS(E1_sdata_cnt[1]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L193, , , , );


--E1_sdata_cnt[0] is U7279:inst|FPGA_7279:inst3|sdata_cnt[0] at LC_X28_Y12_N6
--operation mode is normal

E1_sdata_cnt[0]_lut_out = E1_state.next_delay # !E1_sdata_cnt[0];
E1_sdata_cnt[0] = DFFEAS(E1_sdata_cnt[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L193, , , , );


--E1L148 is U7279:inst|FPGA_7279:inst3|LessThan~111 at LC_X28_Y12_N5
--operation mode is normal

E1L148 = E1_sdata_cnt[1] # E1_sdata_cnt[0];


--E1L201 is U7279:inst|FPGA_7279:inst3|Select~1546 at LC_X29_Y10_N7
--operation mode is normal

E1L201 = !E1_sdata_cnt[2] & !E1L148 & (E1_state.shift_data_high # E1_state.shift_key_high1);


--E1_scmd_cnt[2] is U7279:inst|FPGA_7279:inst3|scmd_cnt[2] at LC_X30_Y10_N8
--operation mode is normal

E1_scmd_cnt[2]_lut_out = E1L188 & (E1L149 $ !E1_scmd_cnt[2] # !E1_state.shift_cmd_high) # !E1L188 & (E1_scmd_cnt[2]);
E1_scmd_cnt[2] = DFFEAS(E1_scmd_cnt[2]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , , , , , );


--E1_scmd_cnt[1] is U7279:inst|FPGA_7279:inst3|scmd_cnt[1] at LC_X30_Y10_N7
--operation mode is normal

E1_scmd_cnt[1]_lut_out = E1_scmd_cnt[1] $ !E1_scmd_cnt[0] # !E1_state.shift_cmd_high;
E1_scmd_cnt[1] = DFFEAS(E1_scmd_cnt[1]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L188, , , , );


--E1_scmd_cnt[0] is U7279:inst|FPGA_7279:inst3|scmd_cnt[0] at LC_X30_Y10_N5
--operation mode is normal

E1_scmd_cnt[0]_lut_out = !E1_scmd_cnt[0] # !E1_state.shift_cmd_high;
E1_scmd_cnt[0] = DFFEAS(E1_scmd_cnt[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L188, , , , );


--E1L202 is U7279:inst|FPGA_7279:inst3|Select~1547 at LC_X29_Y10_N9
--operation mode is normal

E1L202 = !E1_scmd_cnt[2] & !E1_scmd_cnt[0] & !E1_scmd_cnt[1] & E1_state.shift_cmd_high;


--A1L6 is rtl~188 at LC_X29_Y10_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[2]_qfbk = E1_cmd_tmp1[2];
A1L6 = E1_cmd_tmp1[2]_qfbk & !E1_cmd_tmp1[7];

--E1_cmd_tmp1[2] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[2] at LC_X29_Y10_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[2] = DFFEAS(A1L6, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_cmd_tmp[2], , , VCC);


--E1_cmd_tmp1[0] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[0] at LC_X29_Y10_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_cmd_tmp1[0]_lut_out = GND;
E1_cmd_tmp1[0] = DFFEAS(E1_cmd_tmp1[0]_lut_out, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_cmd_tmp[0], , , VCC);


--E1L180 is U7279:inst|FPGA_7279:inst3|process0~0 at LC_X29_Y10_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_start_tmp_qfbk = E1_data_start_tmp;
E1L180 = E1_data_start_tmp_qfbk # A1L6 & E1_cmd_tmp1[0] & !E1_cmd_tmp1[1];

--E1_data_start_tmp is U7279:inst|FPGA_7279:inst3|data_start_tmp at LC_X29_Y10_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_data_start_tmp = DFFEAS(E1L180, !GLOBAL(D2_clk_tmp), VCC, , E1L84, E1_data_start, , , VCC);


--D2_fre_N[0] is U7279:inst|div:inst1|fre_N[0] at LC_X40_Y16_N0
--operation mode is arithmetic

D2_fre_N[0]_lut_out = !D2_fre_N[0];
D2_fre_N[0] = DFFEAS(D2_fre_N[0]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L4 is U7279:inst|div:inst1|fre_N[0]~144 at LC_X40_Y16_N0
--operation mode is arithmetic

D2L4_cout_0 = D2_fre_N[0];
D2L4 = CARRY(D2L4_cout_0);

--D2L5 is U7279:inst|div:inst1|fre_N[0]~144COUT1_180 at LC_X40_Y16_N0
--operation mode is arithmetic

D2L5_cout_1 = D2_fre_N[0];
D2L5 = CARRY(D2L5_cout_1);


--D2_fre_N[1] is U7279:inst|div:inst1|fre_N[1] at LC_X40_Y16_N1
--operation mode is arithmetic

D2_fre_N[1]_lut_out = D2_fre_N[1] $ (D2L4);
D2_fre_N[1] = DFFEAS(D2_fre_N[1]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L7 is U7279:inst|div:inst1|fre_N[1]~148 at LC_X40_Y16_N1
--operation mode is arithmetic

D2L7_cout_0 = !D2L4 # !D2_fre_N[1];
D2L7 = CARRY(D2L7_cout_0);

--D2L8 is U7279:inst|div:inst1|fre_N[1]~148COUT1_181 at LC_X40_Y16_N1
--operation mode is arithmetic

D2L8_cout_1 = !D2L5 # !D2_fre_N[1];
D2L8 = CARRY(D2L8_cout_1);


--D2_fre_N[2] is U7279:inst|div:inst1|fre_N[2] at LC_X40_Y16_N2
--operation mode is arithmetic

D2_fre_N[2]_lut_out = D2_fre_N[2] $ (!D2L7);
D2_fre_N[2] = DFFEAS(D2_fre_N[2]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L10 is U7279:inst|div:inst1|fre_N[2]~152 at LC_X40_Y16_N2
--operation mode is arithmetic

D2L10_cout_0 = D2_fre_N[2] & (!D2L7);
D2L10 = CARRY(D2L10_cout_0);

--D2L11 is U7279:inst|div:inst1|fre_N[2]~152COUT1_182 at LC_X40_Y16_N2
--operation mode is arithmetic

D2L11_cout_1 = D2_fre_N[2] & (!D2L8);
D2L11 = CARRY(D2L11_cout_1);


--D2_fre_N[3] is U7279:inst|div:inst1|fre_N[3] at LC_X40_Y16_N3
--operation mode is arithmetic

D2_fre_N[3]_lut_out = D2_fre_N[3] $ D2L10;
D2_fre_N[3] = DFFEAS(D2_fre_N[3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L13 is U7279:inst|div:inst1|fre_N[3]~156 at LC_X40_Y16_N3
--operation mode is arithmetic

D2L13_cout_0 = !D2L10 # !D2_fre_N[3];
D2L13 = CARRY(D2L13_cout_0);

--D2L14 is U7279:inst|div:inst1|fre_N[3]~156COUT1 at LC_X40_Y16_N3
--operation mode is arithmetic

D2L14_cout_1 = !D2L11 # !D2_fre_N[3];
D2L14 = CARRY(D2L14_cout_1);


--D2L29 is U7279:inst|div:inst1|LessThan~118 at LC_X39_Y16_N2
--operation mode is normal

D2L29 = !D2_fre_N[3] # !D2_fre_N[2] # !D2_fre_N[0] # !D2_fre_N[1];


--D2_fre_N[4] is U7279:inst|div:inst1|fre_N[4] at LC_X40_Y16_N4
--operation mode is arithmetic

D2_fre_N[4]_lut_out = D2_fre_N[4] $ !D2L13;
D2_fre_N[4] = DFFEAS(D2_fre_N[4]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L16 is U7279:inst|div:inst1|fre_N[4]~160 at LC_X40_Y16_N4
--operation mode is arithmetic

D2L16 = D2L17;


--D2_fre_N[5] is U7279:inst|div:inst1|fre_N[5] at LC_X40_Y16_N5
--operation mode is arithmetic

D2_fre_N[5]_carry_eqn = (!D2L16 & GND) # (D2L16 & VCC);
D2_fre_N[5]_lut_out = D2_fre_N[5] $ D2_fre_N[5]_carry_eqn;
D2_fre_N[5] = DFFEAS(D2_fre_N[5]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L20 is U7279:inst|div:inst1|fre_N[5]~164 at LC_X40_Y16_N5
--operation mode is arithmetic

D2L20_cout_0 = !D2L16 # !D2_fre_N[5];
D2L20 = CARRY(D2L20_cout_0);

--D2L21 is U7279:inst|div:inst1|fre_N[5]~164COUT1_183 at LC_X40_Y16_N5
--operation mode is arithmetic

D2L21_cout_1 = !D2L16 # !D2_fre_N[5];
D2L21 = CARRY(D2L21_cout_1);


--D2_fre_N[6] is U7279:inst|div:inst1|fre_N[6] at LC_X40_Y16_N6
--operation mode is arithmetic

D2_fre_N[6]_carry_eqn = (!D2L16 & D2L20) # (D2L16 & D2L21);
D2_fre_N[6]_lut_out = D2_fre_N[6] $ (!D2_fre_N[6]_carry_eqn);
D2_fre_N[6] = DFFEAS(D2_fre_N[6]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , D2L31, );

--D2L23 is U7279:inst|div:inst1|fre_N[6]~168 at LC_X40_Y16_N6
--operation mode is arithmetic

D2L23_cout_0 = D2_fre_N[6] & (!D2L20);
D2L23 = CARRY(D2L23_cout_0);

--D2L24 is U7279:inst|div:inst1|fre_N[6]~168COUT1_184 at LC_X40_Y16_N6
--operation mode is arithmetic