decl7.vhd

八段数码管的显示的小程序,环境是VHDL

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decl7 is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);--地址选择
           led7s : out  STD_LOGIC_VECTOR (6 downto 0));
end decl7;

architecture one of decl7 is
begin
process(a)
begin
case a is
when"00000000"=> led7s<="0111111";
when"00000001"=> led7s<="0000110";
when"00000010"=> led7s<="1011011";
when"00000100"=> led7s<="1001111";
when"00001000"=> led7s<="1100110";
when"00010000"=> led7s<="1101101";
when"00100000"=> led7s<="1111101";
when"01000000"=> led7s<="0000111";
when"10000000"=> led7s<="1111111";
when"11000000"=> led7s<="1101111";
when"00101010"=> led7s<="1110111";
when"01111111"=> led7s<="1111110";
when"00111111"=> led7s<="0111001";
when"00001111"=> led7s<="1011110";
when"00001110"=> led7s<="1111001";
when"00001001"=> led7s<="1110001";
when others=>null;
end case;
end process;
end ;