decl7s.map.qmsg

八段数码管的显示的小程序,环境是VHDL

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 13 18:54:43 2008 " "Info: Processing started: Tue May 13 18:54:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off decl7s -c decl7s " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decl7s -c decl7s" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decl7s.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decl7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decl7s-one " "Info: Found design unit 1: decl7s-one" {  } { { "decl7s.vhd" "" { Text "E:/vhdl code/led/decl7s.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decl7s " "Info: Found entity 1: decl7s" {  } { { "decl7s.vhd" "" { Text "E:/vhdl code/led/decl7s.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "decl7s " "Info: Elaborating entity \"decl7s\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "decl7s.vhd(30) " "Info (10425): VHDL Case Statement information at decl7s.vhd(30): OTHERS choice is never selected" {  } { { "decl7s.vhd" "" { Text "E:/vhdl code/led/decl7s.vhd" 30 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "18 " "Info: Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 13 18:54:45 2008 " "Info: Processing ended: Tue May 13 18:54:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}