decl7s.map.summary

来自「八段数码管的显示的小程序,环境是VHDL」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Tue May 13 18:54:45 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : decl7s
Top-level Entity Name : decl7s
Family : Cyclone
Total logic elements : 7
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0