📄 decl7s.tan.rpt
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Timing Analyzer report for decl7s
Tue May 13 18:55:00 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.168 ns ; a[0] ; led7s[5] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----------+
; N/A ; None ; 11.168 ns ; a[0] ; led7s[5] ;
; N/A ; None ; 11.167 ns ; a[0] ; led7s[4] ;
; N/A ; None ; 11.160 ns ; a[0] ; led7s[1] ;
; N/A ; None ; 11.158 ns ; a[0] ; led7s[6] ;
; N/A ; None ; 11.156 ns ; a[0] ; led7s[3] ;
; N/A ; None ; 11.152 ns ; a[0] ; led7s[0] ;
; N/A ; None ; 10.718 ns ; a[0] ; led7s[2] ;
; N/A ; None ; 10.654 ns ; a[1] ; led7s[5] ;
; N/A ; None ; 10.653 ns ; a[1] ; led7s[4] ;
; N/A ; None ; 10.648 ns ; a[1] ; led7s[3] ;
; N/A ; None ; 10.647 ns ; a[1] ; led7s[6] ;
; N/A ; None ; 10.646 ns ; a[1] ; led7s[1] ;
; N/A ; None ; 10.641 ns ; a[1] ; led7s[0] ;
; N/A ; None ; 10.436 ns ; a[2] ; led7s[3] ;
; N/A ; None ; 10.431 ns ; a[2] ; led7s[5] ;
; N/A ; None ; 10.430 ns ; a[2] ; led7s[6] ;
; N/A ; None ; 10.428 ns ; a[2] ; led7s[0] ;
; N/A ; None ; 10.421 ns ; a[2] ; led7s[4] ;
; N/A ; None ; 10.421 ns ; a[2] ; led7s[1] ;
; N/A ; None ; 10.254 ns ; a[3] ; led7s[3] ;
; N/A ; None ; 10.249 ns ; a[3] ; led7s[5] ;
; N/A ; None ; 10.249 ns ; a[3] ; led7s[4] ;
; N/A ; None ; 10.247 ns ; a[3] ; led7s[6] ;
; N/A ; None ; 10.245 ns ; a[3] ; led7s[0] ;
; N/A ; None ; 10.242 ns ; a[3] ; led7s[1] ;
; N/A ; None ; 10.204 ns ; a[1] ; led7s[2] ;
; N/A ; None ; 9.986 ns ; a[2] ; led7s[2] ;
; N/A ; None ; 9.804 ns ; a[3] ; led7s[2] ;
+-------+-------------------+-----------------+------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Tue May 13 18:55:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decl7s -c decl7s --timing_analysis_only
Info: Longest tpd from source pin "a[0]" to destination pin "led7s[5]" is 11.168 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_144; Fanout = 7; PIN Node = 'a[0]'
Info: 2: + IC(5.926 ns) + CELL(0.114 ns) = 7.509 ns; Loc. = LC_X52_Y20_N9; Fanout = 1; COMB Node = 'Mux~33'
Info: 3: + IC(1.535 ns) + CELL(2.124 ns) = 11.168 ns; Loc. = PIN_156; Fanout = 0; PIN Node = 'led7s[5]'
Info: Total cell delay = 3.707 ns ( 33.19 % )
Info: Total interconnect delay = 7.461 ns ( 66.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 13 18:55:00 2008
Info: Elapsed time: 00:00:01
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