decl7s.fit.summary

来自「八段数码管的显示的小程序,环境是VHDL」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Tue May 13 18:54:52 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : decl7s
Top-level Entity Name : decl7s
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Total logic elements : 7 / 12,060 ( < 1 % )
Total pins : 11 / 173 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )