gh_vme_slave_a32_wi4.vhd

VHDL Library for 8254 timer/counter core

----------------------------------------------------------------

	ACT_IRQ <= '1' when (state_irqA = s1) else
	           '1' when (state_irqB = s1) else
	           '1' when (state_irqC = s1) else
	           '1' when (state_irqD = s1) else
	           '0';
 
	iIVEC <= (x"FFFFFF" & IRQ_VA) when (IRQ_ACK <= "001") else
	         (x"FFFFFF" & IRQ_VB) when (IRQ_ACK <= "010") else
	         (x"FFFFFF" & IRQ_VC) when (IRQ_ACK <= "011") else
	         (x"FFFFFF" & IRQ_VD) when (IRQ_ACK <= "100") else
	          x"FFFFFFFF";

	IRQ_MATCH <= '1' when ((iADD(3 downto 1) = IRQ_LA) and (state_irqA = s1)) else
	             '1' when ((iADD(3 downto 1) = IRQ_LB) and (state_irqB = s1)) else
	             '1' when ((iADD(3 downto 1) = IRQ_LC) and (state_irqC = s1)) else
	             '1' when ((iADD(3 downto 1) = IRQ_LD) and (state_irqD = s1)) else
	             '0';
			  
process(state_IACK,nstate_IACK,iIACKn,iIACK_INn,ACT_IRQ)
begin
case state_IACK is
	when s0 => -- idle 
		IACK_OUTn <= '1';
		if ((iIACKn or iIACK_INn) = '1') then
			nstate_IACK <= s0;
		elsif ((ACT_IRQ = '0') or (IRQ_MATCH = '0')) then 
			nstate_IACK <= s1;
		else
			nstate_IACK <= s2;
		end if;
	when s1 => 
		IACK_OUTn <= iIACK_INn;	
		if (iIACK_INn = '1') then 
			nstate_IACK <= s0;
		else -- 
			nstate_IACK <= s1;
		end if;
	when s2 => 
		IACK_OUTn <= '1';
		if (iDS0n = '0') then 
			nstate_IACK <= s2;
		else
			nstate_IACK <= s0;
		end if;
	when others =>
		IACK_OUTn <= '1';
		nstate_IACK <= s0;
end case;
end process;

process (clk,irst)
begin
	if (irst = '1') then
		IRQ_ACK <= (others => '0');
		iIACK_INn <= '1';
		state_IACK <= s0;
	elsif (rising_edge(clk)) then 
		iIACK_INn <= IACK_INn;
		state_IACK <= nstate_IACK;
		if (iIACKn = '1') then
			IRQ_ACK <= (others => '0');
		elsif (diIACKn = '1') then
			if ((iADD(3 downto 1) = IRQ_LA) and (state_irqA = s1)) then
				IRQ_ACK <= "001";
			elsif ((iADD(3 downto 1) = IRQ_LB) and (state_irqB = s1)) then
				IRQ_ACK <= "010";
			elsif ((iADD(3 downto 1) = IRQ_LC) and (state_irqC = s1)) then
				IRQ_ACK <= "011";
			elsif ((iADD(3 downto 1) = IRQ_LD) and (state_irqD = s1)) then
				IRQ_ACK <= "100";
			end if;
		else
			IRQ_ACK <= IRQ_ACK;
		end if;
	end if;		
end process;

----------------------------------------------------------------

	IRQn <= (not iIRQ);

	iIRQ(1) <= '1' when ((state_irqA = s1) and (IRQ_LA = "001")) else
	           '1' when ((state_irqB = s1) and (IRQ_LB = "001")) else
	           '1' when ((state_irqC = s1) and (IRQ_LC = "001")) else
	           '1' when ((state_irqD = s1) and (IRQ_LD = "001")) else
	           '0';

	iIRQ(2) <= '1' when ((state_irqA = s1) and (IRQ_LA = "010")) else
	           '1' when ((state_irqB = s1) and (IRQ_LB = "010")) else
	           '1' when ((state_irqC = s1) and (IRQ_LC = "010")) else
	           '1' when ((state_irqD = s1) and (IRQ_LD = "010")) else
	           '0';

	iIRQ(3) <= '1' when ((state_irqA = s1) and (IRQ_LA = "011")) else
	           '1' when ((state_irqB = s1) and (IRQ_LB = "011")) else
	           '1' when ((state_irqC = s1) and (IRQ_LC = "011")) else
	           '1' when ((state_irqD = s1) and (IRQ_LD = "011")) else
	           '0';

	iIRQ(4) <= '1' when ((state_irqA = s1) and (IRQ_LA = "100")) else
	           '1' when ((state_irqB = s1) and (IRQ_LB = "100")) else
	           '1' when ((state_irqC = s1) and (IRQ_LC = "100")) else
	           '1' when ((state_irqD = s1) and (IRQ_LD = "100")) else
	           '0';

	iIRQ(5) <= '1' when ((state_irqA = s1) and (IRQ_LA = "101")) else
	           '1' when ((state_irqB = s1) and (IRQ_LB = "101")) else
	           '1' when ((state_irqC = s1) and (IRQ_LC = "101")) else
	           '1' when ((state_irqD = s1) and (IRQ_LD = "101")) else
	           '0';

	iIRQ(6) <= '1' when ((state_irqA = s1) and (IRQ_LA = "110")) else
	           '1' when ((state_irqB = s1) and (IRQ_LB = "110")) else
	           '1' when ((state_irqC = s1) and (IRQ_LC = "110")) else
	           '1' when ((state_irqD = s1) and (IRQ_LD = "110")) else
	           '0';

----------------------------------------------------------------
-----------  IRQ A ---------------------------------------------

process(state_irqA,nstate_irqA,iIRQA,state_IACK,state,IRQ_ACK,iDS0n)
begin
case state_irqA is
	when s0 => -- idle
		if (iIRQA = x"01") then
			nstate_irqA <= s1;
		else
			nstate_irqA <= s0;
		end if;
	when s1 =>
		if (state_IACK = s0) then 
			nstate_irqA <= s1;
		elsif ((state = s7) and (IRQ_ACK = "001") and (iDS0n = '1')) then 
			nstate_irqA <= s0;
		else
			nstate_irqA <= s1;
		end if;
	when others =>
		nstate_irqA <= s0;
end case;
end process;

process (clk,irst)
begin
	if (irst = '1') then
		iIRQA <= (others => '0');
		state_irqA <= s0;
	elsif (rising_edge(clk)) then
		iIRQA(0) <= g_IRQA;
		iIRQA(1) <= iIRQA(0);
		if (IRQ_LA = "000") then
			state_irqA <= s0;
		else
			state_irqA <= nstate_irqA;
		end if;
	end if;		
end process;

----------------------------------------------------------------
-----------  IRQ B ---------------------------------------------

process(state_irqB,nstate_irqB,iIRQB,state_IACK,state,IRQ_ACK,iDS0n)
begin
case state_irqB is
	when s0 => -- idle
		if (iIRQB = x"01") then
			nstate_irqB <= s1;
		else
			nstate_irqB <= s0;
		end if;
	when s1 =>
		if (state_IACK = s0) then 
			nstate_irqB <= s1;
		elsif ((state = s7) and (IRQ_ACK = "010") and (iDS0n = '1')) then 
			nstate_irqB <= s0;
		else
			nstate_irqB <= s1;
		end if;
	when others =>
		nstate_irqB <= s0;
end case;
end process;

process (clk,irst)
begin
	if (irst = '1') then
		iIRQB <= (others => '0');
		state_irqB <= s0;
	elsif (rising_edge(clk)) then
		iIRQB(0) <= g_IRQB;
		iIRQB(1) <= iIRQB(0);
		if (IRQ_LB = "000") then
			state_irqB <= s0;
		else
			state_irqB <= nstate_irqB;
		end if;
	end if;		
end process;

----------------------------------------------------------------
-----------  IRQ C ---------------------------------------------

process(state_irqC,nstate_irqC,iIRQC,state_IACK,state,IRQ_ACK,iDS0n)
begin
case state_irqC is
	when s0 => -- idle
		if (iIRQC = x"01") then
			nstate_irqC <= s1;
		else
			nstate_irqC <= s0;
		end if;
	when s1 =>
		if (state_IACK = s0) then 
			nstate_irqC <= s1;
		elsif ((state = s7) and (IRQ_ACK = "011") and (iDS0n = '1')) then 
			nstate_irqC <= s0;
		else
			nstate_irqC <= s1;
		end if;
	when others =>
		nstate_irqC <= s0;
end case;
end process;

process (clk,irst)
begin
	if (irst = '1') then
		iIRQC <= (others => '0');
		state_irqC <= s0;
	elsif (rising_edge(clk)) then
		iIRQC(0) <= g_IRQC;
		iIRQC(1) <= iIRQC(0);
		if (IRQ_LC = "000") then
			state_irqC <= s0;
		else
			state_irqC <= nstate_irqC;
		end if;
	end if;		
end process;

----------------------------------------------------------------
-----------  IRQ D ---------------------------------------------

process(state_irqD,nstate_irqD,iIRQD,state_IACK,state,IRQ_ACK,iDS0n)
begin
case state_irqD is
	when s0 => -- idle
		if (iIRQD = x"01") then
			nstate_irqD <= s1;
		else
			nstate_irqD <= s0;
		end if;
	when s1 =>
		if (state_IACK = s0) then 
			nstate_irqD <= s1;
		elsif ((state = s7) and (IRQ_ACK = "100") and (iDS0n = '1')) then 
			nstate_irqD <= s0;
		else
			nstate_irqD <= s1;
		end if;
	when others =>
		nstate_irqD <= s0;
end case;
end process;

process (clk,irst)
begin
	if (irst = '1') then
		iIRQD <= (others => '0');
		state_irqD <= s0;
	elsif (rising_edge(clk)) then
		iIRQD(0) <= g_IRQD;
		iIRQD(1) <= iIRQD(0);
		if (IRQ_LD = "000") then
			state_irqD <= s0;
		else
			state_irqD <= nstate_irqD;
		end if;
	end if;		
end process;

-------------------------------------------------

end architecture;