cstartup_sam9.c

this document is source code for arm9 of atmel

 //  ----------------------------------------------------------------------------
 //          ATMEL Microcontroller Software Support  -  ROUSSET  -
 //  ----------------------------------------------------------------------------
 //  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 //  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 //  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 //  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 //  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 //  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 //  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 //  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 //  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 //  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //  ----------------------------------------------------------------------------
//*----------------------------------------------------------------------------
//* File Name           : Cstartup_SAM9.c
//* Object              : Low level initializations written in C for IAR
//*                       tools
//* Creation            : 12/Jun/04
//* 1.2   28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL
//* 1.3   20/Feb/06     : Suppress DBGU initialization
//*----------------------------------------------------------------------------

// Include the board file description
#include "board.h"

// The following functions must be write in ARM mode this function called directly
// by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);
//*--------------------------------------------------------------------------------------
//* Function Name       : AT91F_InitSdram
//* Object              : Initialize the SDRAM
//*--------------------------------------------------------------------------------------
void AT91F_InitSDRAM (void)
{
	unsigned int i;
	AT91PS_SDRAMC	psdrc = AT91C_BASE_SDRAMC;
	AT91F_SDRAMC_CfgPIO();
	psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9  |
						AT91C_SDRAMC_NR_13 |
						AT91C_SDRAMC_CAS_2 |
						AT91C_SDRAMC_NB_4_BANKS |
						AT91C_SDRAMC_DBW_32_BITS |
						AT91C_SDRAMC_TWR_2 |
						AT91C_SDRAMC_TRC_7 |
						AT91C_SDRAMC_TRP_2 |
						AT91C_SDRAMC_TRCD_2 |
						AT91C_SDRAMC_TRAS_5 |
						AT91C_SDRAMC_TXSR_8 ;

	for (i =0; i< 1000;i++);

	psdrc->SDRAMC_MR	= 0x00000002;		// Set PRCHG AL
	*AT91C_SDRAM	= 0x00000000;			// Perform PRCHG

	for (i =0; i< 10000;i++);

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
	*(AT91C_SDRAM+4)	= 0x00000001;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 2 CBR
	*(AT91C_SDRAM+8)	= 0x00000002;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 3 CBR
	*(AT91C_SDRAM+0xc)	= 0x00000003;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 4 CBR
	*(AT91C_SDRAM+0x10)	= 0x00000004;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 5 CBR
	*(AT91C_SDRAM+0x14)	= 0x00000005;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 6 CBR
	*(AT91C_SDRAM+0x18)	= 0x00000006;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 7 CBR
	*(AT91C_SDRAM+0x1c)	= 0x00000007;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 8 CBR
	*(AT91C_SDRAM+0x20)	= 0x00000008;	// Perform CBR

	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		// Set LMR operation
	*(AT91C_SDRAM+0x24)	= 0xcafedede;						// Perform LMR burst=1, lat=2

	psdrc->SDRAMC_TR	= (AT91C_MASTER_CLOCK * 7)/1000000;	// Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
										// (F : system clock freq. MHz
	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		// Set Normal mode
	*AT91C_SDRAM	= 0x00000000;	// Perform Normal mode

//	psdrc->SDRAMC_HSR	= AT91C_SDRAMC_DA_ENABLE;		// Set Decode Cycle NECESAIRE pour NADIA a 22MHz 25aug03
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//*        this function can be use a Stack, depending the compilation
//*        optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void) @ "ICODE"
{
 int            i;
 volatile unsigned int test;
 AT91PS_PMC     pPMC = AT91C_BASE_PMC;
AT91PS_MATRIX	pHmatrix = AT91C_BASE_MATRIX;
    //* Watchdog Disable
        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;

	pHmatrix->MATRIX_EBICSA |= 0x1003A;
        //remap PDC
	//pHmatrix->MATRIX_MCFG |= (0x1 << 2);
	//* Set MCK at 47 923 200
    // 1 Enabling the Main Oscillator:
        // SCK = 1/32768 = 30.51 uSeconde
    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
    pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
        // Wait the startup time
    while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
	// 2 Checking the Main Oscillator Frequency (Optional)
	// 3 Setting PLL and divider:
	pPMC->PMC_PLLBR = 0x10483F0E ;

    // Wait the startup time
    while(!(pPMC->PMC_SR & AT91C_PMC_LOCKB));
 	// 4. Selection of Master Clock and Processor Clock
 	// select the PLL clock divided by 2 for MCK only
 	pPMC->PMC_MCKR =  AT91C_PMC_MDIV_2 | AT91C_PMC_CSS_PLLB_CLK;
 	while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));


	// Set up the default interrupts handler vectors
	AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
	for (i=1;i < 31; i++)
	{
	    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
	}
	AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;

    AT91F_InitSDRAM ();
}