serial.map.rpt

-- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --

; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path       ;
+----------------------------------+-----------------+------------------------------------+------------------------------------+
; serial.bdf                       ; yes             ; User Block Diagram/Schematic File  ; G:/Q71/VHDL/serial/serial.bdf      ;
; serial_test.vhd                  ; yes             ; User VHDL File                     ; G:/Q71/VHDL/serial/serial_test.vhd ;
+----------------------------------+-----------------+------------------------------------+------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 93    ;
;                                             ;       ;
; Total combinational functions               ; 93    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 51    ;
;     -- 3 input functions                    ; 12    ;
;     -- <=2 input functions                  ; 30    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 78    ;
;     -- arithmetic mode                      ; 15    ;
;                                             ;       ;
; Total registers                             ; 55    ;
;     -- Dedicated logic registers            ; 55    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 13    ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 55    ;
; Total fan-out                               ; 487   ;
; Average fan-out                             ; 3.02  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
; |serial                    ; 93 (0)            ; 55 (0)       ; 0           ; 0            ; 0       ; 0         ; 13   ; 0            ; |serial                  ; work         ;
;    |serial_test:inst|      ; 93 (93)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |serial|serial_test:inst ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; serial_test:inst|txd_buf[7]           ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 55    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 55    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 13    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; serial_test:inst|txd_reg               ; 4       ;
; serial_test:inst|txd_buf[0]            ; 2       ;
; serial_test:inst|txd_buf[1]            ; 1       ;
; serial_test:inst|txd_buf[2]            ; 1       ;
; serial_test:inst|txd_buf[4]            ; 2       ;
; serial_test:inst|txd_buf[5]            ; 1       ;
; serial_test:inst|txd_buf[6]            ; 1       ;
; Total number of inverted registers = 7 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; 12:1               ; 3 bits    ; 24 LEs        ; 6 LEs                ; 18 LEs                 ; Yes        ; |serial|serial_test:inst|txd_buf[1] ;
; 19:1               ; 2 bits    ; 24 LEs        ; 10 LEs               ; 14 LEs                 ; Yes        ; |serial|serial_test:inst|txd_buf[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jun 12 12:28:10 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial
Info: Found 1 design units, including 1 entities, in source file serial.bdf
    Info: Found entity 1: serial
Info: Found 2 design units, including 1 entities, in source file serial_test.vhd
    Info: Found design unit 1: serial_test-arch
    Info: Found entity 1: serial_test
Info: Elaborating entity "serial" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "serial" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "serial_test" for hierarchy "serial_test:inst"
Warning (10036): Verilog HDL or VHDL warning at serial_test.vhd(50): object "key_entry2" assigned a value but never read
Warning (14130): Reduced register "serial_test:inst|txd_buf[7]" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 116 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 10 output pins
    Info: Implemented 103 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Thu Jun 12 12:28:14 2008
    Info: Elapsed time: 00:00:04