pdiusb.vhd

USB与FPGA接口的程序设计。里面是所有的源文件都经本人测试可以用

library IEEE;
use IEEE.std_logic_1164.all;
entity PDIUSB is
	port(
		vm : in STD_LOGIC;
		vp : in STD_LOGIC;
		S0 : out STD_LOGIC;
		S1 : out STD_LOGIC;
		S2 : out STD_LOGIC;
		S3 : out STD_LOGIC;
		S4 : out STD_LOGIC;
		S5 : out STD_LOGIC;
		S6 : out STD_LOGIC;
		fse0 : out STD_LOGIC;
		oe : out STD_LOGIC;
		vpo : out STD_LOGIC
		);
end PDIUSB;

architecture SIM of PDIUSB is
	---- 部件定义 -----
	component SRAM
		generic(
			fname : STRING
			);
		port (
			A : in STD_LOGIC_VECTOR (14 downto 0);
			CE : in STD_LOGIC;
			OE : in STD_LOGIC;
			WE : in STD_LOGIC;
			D : inout STD_LOGIC_VECTOR (7 downto 0)
			);
	end component;
	component te
		port (
			clk : in STD_LOGIC;
			ea : in STD_LOGIC;
			rst : in STD_LOGIC;
			Port1 : out STD_LOGIC_VECTOR (7 downto 0);
			Port2 : out STD_LOGIC_VECTOR (7 downto 0);
			Port3 : out STD_LOGIC_VECTOR (7 downto 0);
			ale : out STD_LOGIC;
			psen : out STD_LOGIC;
			Port0 : inout STD_LOGIC_VECTOR (7 downto 0)
			);
	end component;
	component FPGA
		port (
			ALE : in STD_LOGIC;
			OSC : in STD_LOGIC;
			P2 : in STD_LOGIC_VECTOR (7 downto 0);
			PC_D : in STD_LOGIC_VECTOR (7 downto 0);
			PSEN : in STD_LOGIC;
			RD : in STD_LOGIC;
			T0 : in STD_LOGIC;
			TXD : in STD_LOGIC;
			WR : in STD_LOGIC;
			A : out STD_LOGIC_VECTOR (7 downto 0);
			CE : out STD_LOGIC;
			OE : out STD_LOGIC;
			RST : out STD_LOGIC;
			S : out STD_LOGIC_VECTOR (6 downto 0);
			XTAL1 : out STD_LOGIC;
			P0 : inout STD_LOGIC_VECTOR (7 downto 0);
			P1 : inout STD_LOGIC_VECTOR (7 downto 0)
			);
	end component;
	---- 用户数据表定义 -----
	constant fname: STRING:= "..\usb\firmware.hex";
	---- 常量 -----
	constant GND_CONSTANT   : STD_LOGIC := '0';
	---- 信号定义 ----
	signal A : STD_LOGIC_VECTOR (15 downto 0);
	signal AD : STD_LOGIC_VECTOR (7 downto 0);
	signal P1 : STD_LOGIC_VECTOR (7 downto 0);
	signal P3 : STD_LOGIC_VECTOR (7 downto 0);
	signal S : STD_LOGIC_VECTOR (6 downto 0);
	signal NET3634 : STD_LOGIC;
	signal NET3641 : STD_LOGIC;
	signal NET3791 : STD_LOGIC;
	signal NET3795 : STD_LOGIC;
	signal NET3799 : STD_LOGIC;
	signal NET3803 : STD_LOGIC;
	---- 信号地定义 -----
	signal GND : STD_LOGIC;
	---- 全局信号定义 -----
	signal OSC : STD_LOGIC;
	signal PC_D : STD_LOGIC_VECTOR (7 downto 0);
	
begin
	----- 声明0----
	process
	begin
		osc<= '0', '1' after 10ns;
		wait for 21ns;
	end process;
	
	PC_D(0)<= '1', '0' after 500ns;
	----部件初始化----
	Ufpga : FPGA
	port map(
		A(0) => A(0),
		A(1) => A(1),
		A(2) => A(2),
		A(3) => A(3),
		A(4) => A(4),
		A(5) => A(5),
		A(6) => A(6),
		A(7) => A(7),
		ALE => NET3799,
		CE => NET3641,
		OE => NET3634,
		OSC => OSC,
		P0 => AD,
		P1 => P1,
		P2(0) => A(8),
		P2(1) => A(9),
		P2(2) => A(10),
		P2(3) => A(11),
		P2(4) => A(12),
		P2(5) => A(13),
		P2(6) => A(14),
		P2(7) => A(15),
		PC_D => PC_D,
		PSEN => NET3803,
		RD => P3(7),
		RST => NET3795,
		S => S,
		T0 => P3(4),
		TXD => P3(1),
		WR => P3(6),
		XTAL1 => NET3791
		);
	Uram : SRAM
	generic map (
		fname => fname
		)
	port map(
		A(0) => A(0),
		A(1) => A(1),
		A(2) => A(2),
		A(3) => A(3),
		A(4) => A(4),
		A(5) => A(5),
		A(6) => A(6),
		A(7) => A(7),
		A(8) => A(8),
		A(9) => A(9),
		A(10) => A(10),
		A(11) => A(11),
		A(12) => A(12),
		A(13) => A(13),
		A(14) => A(14),
		CE => NET3641,
		D => AD,
		OE => NET3634,
		WE => P3(6)
		);
	Uuc : te
	port map(
		Port2(0) => A(8),
		Port2(1) => A(9),
		Port2(2) => A(10),
		Port2(3) => A(11),
		Port2(4) => A(12),
		Port2(5) => A(13),
		Port2(6) => A(14),
		Port2(7) => A(15),
		Port0 => AD,
		Port1 => P1,
		Port3 => P3,
		ale => NET3799,
		clk => NET3791,
		ea => GND,
		psen => NET3803,
		rst => NET3795
		);
	---- 电源、地管脚指定----
	GND <= GND_CONSTANT;
	
	-- 输入信号
	P1(1) <= vm;
	P1(0) <= vp;
	
	-- 输出缓存
	S0 <= S(0);
	S1 <= S(1);
	S2 <= S(2);
	S3 <= S(3);
	S4 <= S(4);
	S5 <= S(5);
	S6 <= S(6);
	fse0 <= P1(3);
	oe <= P1(4);
	vpo <= P1(2);
end SIM;