clk.vhd

USB与FPGA接口的程序设计。里面是所有的源文件都经本人测试可以用

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLK is
	port(
		clk:  in  STD_LOGIC; -- 48MHz输入时钟
		rst:  in  STD_LOGIC; -- 异步复位
		clko: out STD_LOGIC; -- 24MHz输出时钟
		rsto: out STD_LOGIC  -- 复位
		);
end CLK;

--------------------------------------------------------------------------------
architecture BHV of CLK is
	signal div: STD_LOGIC;
begin
	clko<= div;
	rsto<= rst;
	
	process(clk, rst)              --2分频
	begin
		if rst= '1' then
			div<= '0';
		elsif rising_edge(clk) then
			div<= not(div);
		end if;
	end process;
	
end BHV;