testusb.vhd

USB与FPGA接口的程序设计。里面是所有的源文件都经本人测试可以用

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity TestUSB is
end TestUSB;

architecture Test of TestUSB is
	component USB
		port(
			-- usb接口
			vp:    in  STD_LOGIC;
			vm:    in  STD_LOGIC;
			vpo:   out STD_LOGIC;
			fse0:  out STD_LOGIC;
			oe:    out STD_LOGIC;
			-- LED7段码
			S0:    out STD_LOGIC;
			S1:    out STD_LOGIC;
			S2:    out STD_LOGIC;
			S3:    out STD_LOGIC;
			S4:    out STD_LOGIC;
			S5:    out STD_LOGIC;
			S6:    out STD_LOGIC
			);
	end component;
	
	--------------------
	-- UUT信号
	signal vp:        STD_LOGIC;
	signal vm:        STD_LOGIC;
	signal vpo:       STD_LOGIC;
	signal fse0:      STD_LOGIC;
	signal oe:        STD_LOGIC;
	
	--------------------
	--测试控制信号 
	signal clk48:     STD_LOGIC;
	signal rst:       STD_LOGIC;
	signal tb_xd:     STD_LOGIC;
	signal tb_x0:     STD_LOGIC;
	signal tb_clk:    STD_LOGIC;
	signal sim:       STD_LOGIC;
	signal stim:      STD_LOGIC;
	
	--------------------
	-- 基准信号
	signal urxd:      STD_LOGIC;
	signal urx0:      STD_LOGIC;
	signal utxd:      STD_LOGIC;
	signal utx0:      STD_LOGIC;
	signal utxoe:     STD_LOGIC;
	
begin
	
	--------------------
	-- PDIUSB芯片
	vp   <= urxd      when urx0= '0' else '0';
	vm   <= not(urxd) when urx0= '0' else '0';
	utxd <= vpo;
	utx0 <= fse0;
	utxoe<= oe;
	
	--------------------
	Uctrl: usbctrl port map(
		sim=> sim,
		stim=> stim,
		clk48=> clk48,
		rst=> rst,
		tb_xd=> tb_xd,
		tb_x0=> tb_x0,
		tb_clk=> tb_clk,
		uut_txd=> utxd,
		uut_tx0=> utx0,
		uut_rxd=> urxd,
		uut_rx0=> urx0
		);
	
	--------------------
	UUT: PDIUSB port map(
		vp  => vp,
		vm  => vm,
		vpo => vpo,
		fse0=> fse0,
		oe  => oe);
	
	sim<= '1', '0' after 60us;
	
	--------------------
	process
	begin
		wait for 5us;
		
		--------------------
		GetDeviceDescriptor(tb_clk, tb_xd, tb_x0, stim);
		GetConfigDescriptor(tb_clk, tb_xd, tb_x0, stim);
		GetStringDescriptor(tb_clk, tb_xd, tb_x0, stim);
		SetAddress         (tb_clk, tb_xd, tb_x0, stim);
		SetConfiguration   (tb_clk, tb_xd, tb_x0, stim);
		GetStatus          (tb_clk, tb_xd, tb_x0, stim);
		GetReport          (tb_clk, tb_xd, tb_x0, stim);
		GetClassDescriptor (tb_clk, tb_xd, tb_x0, stim);
		InvalidRequest     (tb_clk, tb_xd, tb_x0, stim);
		
		--------------------
		stim<= '0';
		
		wait for 5us;
		
		assert FALSE
		report "successful end of simulation"
		severity FAILURE;
		
		wait;
	end process;
	
end Test;