sim_file_list.lst

来自「VHDL MAC wishbone VHDL MAC wishbone」· LST 代码 · 共 15 行

../../../bench/verilog/tb_ethernet.v
../../../bench/verilog/tb_eth_defines.v
../../../bench/verilog/eth_phy.v
../../../bench/verilog/eth_phy_defines.v
../../../bench/verilog/wb_bus_mon.v
../../../bench/verilog/wb_slave_behavioral.v
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../../../lib/artisan/art_hssp_256x32_bist.v
../../../../../lib/artisan/art_hssp_256x32/art_hssp_256x32.v
../../../../../bist/rtl/verilog/bist.v
../../../../../bist/rtl/verilog/bist_sp_top.v