edge.map.qmsg

图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 03 13:26:18 2009 " "Info: Processing started: Tue Mar 03 13:26:18 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off edge -c edge " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off edge -c edge" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "edgewen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file edgewen.v" { { "Info" "ISGN_ENTITY_NAME" "1 edgewen " "Info: Found entity 1: edgewen" {  } { { "edgewen.v" "" { Text "F:/sopc/lunwen/edge/edgewen.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_abs1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lpm_abs1.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs1 " "Info: Found entity 1: lpm_abs1" {  } { { "lpm_abs1.v" "" { Text "F:/sopc/lunwen/edge/lpm_abs1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "edge.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file edge.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 edge " "Info: Found entity 1: edge" {  } { { "edge.bdf" "" { Schematic "F:/sopc/lunwen/edge/edge.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cordic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cordic.v" { { "Info" "ISGN_ENTITY_NAME" "1 cordic " "Info: Found entity 1: cordic" {  } { { "cordic.v" "" { Text "F:/sopc/lunwen/edge/cordic.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "edge " "Info: Elaborating entity \"edge\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "edgewen inst " "Warning: Block or symbol \"edgewen\" of instance \"inst\" overlaps another block or symbol" {  } { { "edge.bdf" "" { Schematic "F:/sopc/lunwen/edge/edge.bdf" { { 72 216 424 200 "inst" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "edgewen edgewen:inst " "Info: Elaborating entity \"edgewen\" for hierarchy \"edgewen:inst\"" {  } { { "edge.bdf" "inst" { Schematic "F:/sopc/lunwen/edge/edge.bdf" { { 72 216 424 200 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 22 edgewen.v(143) " "Warning (10230): Verilog HDL assignment warning at edgewen.v(143): truncated value with size 23 to match size of target (22)" {  } { { "edgewen.v" "" { Text "F:/sopc/lunwen/edge/edgewen.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub edgewen:inst\|lpm_add_sub:lpm_add_sub1 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"edgewen:inst\|lpm_add_sub:lpm_add_sub1\"" {  } { { "edgewen.v" "lpm_add_sub1" { Text "F:/sopc/lunwen/edge/edgewen.v" 70 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "edgewen:inst\|lpm_add_sub:lpm_add_sub1 " "Info: Elaborated megafunction instantiation \"edgewen:inst\|lpm_add_sub:lpm_add_sub1\"" {  } { { "edgewen.v" "" { Text "F:/sopc/lunwen/edge/edgewen.v" 70 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "edgewen:inst\|lpm_add_sub:lpm_add_sub1 " "Info: Instantiated megafunction \"edgewen:inst\|lpm_add_sub:lpm_add_sub1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 11 " "Info: Parameter \"lpm_width\" = \"11\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Info: Parameter \"lpm_representation\" = \"SIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction SUB " "Info: Parameter \"lpm_direction\" = \"SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "edgewen.v" "" { Text "F:/sopc/lunwen/edge/edgewen.v" 70 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_1te.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_1te.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_1te " "Info: Found entity 1: add_sub_1te" {  } { { "db/add_sub_1te.tdf" "" { Text "F:/sopc/lunwen/edge/db/add_sub_1te.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_1te edgewen:inst\|lpm_add_sub:lpm_add_sub1\|add_sub_1te:auto_generated " "Info: Elaborating entity \"add_sub_1te\" for hierarchy \"edgewen:inst\|lpm_add_sub:lpm_add_sub1\|add_sub_1te:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_abs1 edgewen:inst\|lpm_abs1:tem1 " "Info: Elaborating entity \"lpm_abs1\" for hierarchy \"edgewen:inst\|lpm_abs1:tem1\"" {  } { { "edgewen.v" "tem1" { Text "F:/sopc/lunwen/edge/edgewen.v" 94 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lpm_abs1.v(24) " "Warning (10230): Verilog HDL assignment warning at lpm_abs1.v(24): truncated value with size 32 to match size of target (1)" {  } { { "lpm_abs1.v" "" { Text "F:/sopc/lunwen/edge/lpm_abs1.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 lpm_abs1.v(25) " "Warning (10230): Verilog HDL assignment warning at lpm_abs1.v(25): truncated value with size 32 to match size of target (11)" {  } { { "lpm_abs1.v" "" { Text "F:/sopc/lunwen/edge/lpm_abs1.v" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "a_int lpm_abs1.v(16) " "Warning (10240): Verilog HDL Always Construct warning at lpm_abs1.v(16): inferring latch(es) for variable \"a_int\", which holds its previous value in one or more paths through the always construct" {  } { { "lpm_abs1.v" "" { Text "F:/sopc/lunwen/edge/lpm_abs1.v" 16 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "i lpm_abs1.v(16) " "Warning (10240): Verilog HDL Always Construct warning at lpm_abs1.v(16): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" {  } { { "lpm_abs1.v" "" { Text "F:/sopc/lunwen/edge/lpm_abs1.v" 16 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult edgewen:inst\|lpm_mult:lpm_multe " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"edgewen:inst\|lpm_mult:lpm_multe\"" {  } { { "edgewen.v" "lpm_multe" { Text "F:/sopc/lunwen/edge/edgewen.v" 112 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "edgewen:inst\|lpm_mult:lpm_multe " "Info: Elaborated megafunction instantiation \"edgewen:inst\|lpm_mult:lpm_multe\"" {  } { { "edgewen.v" "" { Text "F:/sopc/lunwen/edge/edgewen.v" 112 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}