edgewen.v.bak

图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换

module edgewen(out_data1,out_data2,out_data3,out_data14,out_data15,in_data1,in_data2,in_data3,clk);// in_data21,in_data31,in_data41,
output[10:0] out_data1;
output[21:0] out_data2;
output[21:0] out_data3;

output[10:0] out_data14;
output[10:0] out_data15;

input [7:0] in_data1,in_data2,in_data3;
input clk;

reg[10:0] out_data14;
reg[10:0] out_data15;
reg[10:0]  out_data1;
reg[21:0]  out_data2,out_data3;//out_data3;

reg [7:0]  temp_data1,temp_data2,temp_data3;
reg [7:0]  temp_data4,temp_data5,temp_data6;
reg [7:0]  temp_data7,temp_data8,temp_data9;

reg [9:0]  temp_data10,temp_data11;
reg [10:0] sign_temp_data10,sign_temp_data12;

reg [9:0]  temp_data12,temp_data13;
reg [10:0] sign_temp_data11,sign_temp_data13;


wire [10:0]  temp_data14,temp_data15;

//reg[19:0] lv,ly;
wire[22:0] lv_temp;
wire[22:0] lv2,ly2;


wire[10:0]  temp_wire1,temp_wire2;
wire[21:0]  temp_wire3;
always @(posedge clk)
begin
  temp_data1<=in_data1;
  temp_data2<=in_data2;
  temp_data3<=in_data3;
end
always @(posedge clk)
begin
  temp_data4<=temp_data1;
  temp_data5<=temp_data2;
  temp_data6<=temp_data3;
end
always @(posedge clk)
begin
  temp_data7<=temp_data4;
  temp_data8<=temp_data5;
  temp_data9<=temp_data6;
end
always @(posedge clk)
begin
 temp_data10<={1'b0,temp_data1}+{temp_data4,1'b0}+{1'b0,temp_data7};//three 8 to 10
// temp_data11<={1'b0,temp_data2}+{temp_data5,1'b0}+{1'b0,temp_data8};
 temp_data11<={1'b0,temp_data3}+{temp_data6,1'b0}+{1'b0,temp_data9};
 
 sign_temp_data10<={1'b0,temp_data10};  //change to signed 11
 sign_temp_data11<={1'b0,temp_data11};
 /*lpm_add_sub lpm_add_sub1(.result(temp_data14),.dataa(sign_temp_data11),.datab(sign_temp_data10));
   defparam lpm_add_sub1.lpm_width =11;
   defparam lpm_add_sub1.lpm_representation = "SIGNED";
   defparam lpm_add_sub1.lpm_direction  = "SUB" ;*/
   
 //temp_data14<= temp_data11-temp_data10;
end
lpm_add_sub lpm_add_sub1(.result(temp_data14),.dataa(sign_temp_data11),.datab(sign_temp_data10));
   defparam lpm_add_sub1.lpm_width =11;
   defparam lpm_add_sub1.lpm_representation = "SIGNED";
   defparam lpm_add_sub1.lpm_direction  = "SUB" ;//signed11  sub
  
always @(posedge clk)
begin
 temp_data12<={1'b0,temp_data1}+{temp_data2,1'b0}+{1'b0,temp_data3};
// temp_data11<={1'b0,temp_data4}+{temp_data5,1'b0}+{1'b0,temp_data6};
 temp_data13<={1'b0,temp_data7}+{temp_data8,1'b0}+{1'b0,temp_data9};
 sign_temp_data12<={1'b0,temp_data12};
 sign_temp_data13<={1'b0,temp_data13};
 /*lpm_add_sub lpm_add_sub2(.result(temp_data15),.dataa(sign_temp_data13),.datab(sign_temp_data12));
   defparam lpm_add_sub2.lpm_width =11;
   defparam lpm_add_sub2.lpm_representation = "SIGNED";
   defparam lpm_add_sub2.lpm_direction  = "SUB" ;*/
 
// temp_data15<= temp_data13-temp_data12;
end
lpm_add_sub lpm_add_sub2(.result(temp_data15),.dataa(sign_temp_data12),.datab(sign_temp_data13));
   defparam lpm_add_sub2.lpm_width =11;
   defparam lpm_add_sub2.lpm_representation = "SIGNED";
   defparam lpm_add_sub2.lpm_direction  = "SUB" ;

lpm_abs1 tem1(.result(temp_wire1),.data(temp_data14));
  defparam tem1.lpm_width=11; 
lpm_abs1 tem2(.result(temp_wire2),.data(temp_data15));
 defparam tem2.lpm_width=11;

/*lpm_mult lpm_multe(.dataa(temp_data14),.datab(temp_data15),.result(lv_temp));
  defparam lpm_multe.lpm_widtha=11;
  defparam lpm_multe.lpm_widthb=11;
  defparam lpm_multe.lpm_widths=11;
  defparam lpm_multe.lpm_widthp=22;
  defparam lpm_multe.lpm_representation  = "SIGNED";*/
lpm_mult	lpm_multe (
				.dataa (temp_data14),
				.datab (temp_data15),
				.result (lv_temp),
				.aclr (1'b0),
				.clken (1'b1),
				.clock (1'b0),
				.sum (1'b0));
	defparam
		lpm_multe.lpm_hint = "MAXIMIZE_SPEED=5",
		lpm_multe.lpm_representation = "SIGNED",
		lpm_multe.lpm_type = "LPM_MULT",
		lpm_multe.lpm_widtha = 11,
		lpm_multe.lpm_widthb = 11,
		lpm_multe.lpm_widthp = 22;
  
lpm_mult lpm_multe1(.dataa(temp_data14),.datab(temp_data14),.result(lv2));
  defparam lpm_multe1.lpm_widtha=11;
  defparam lpm_multe1.lpm_widthb=11;
  defparam lpm_multe1.lpm_widths=11;
  defparam lpm_multe1.lpm_widthp=22;
  defparam lpm_multe1.lpm_representation  = "SIGNED";
  
 lpm_mult lpm_multe2(.dataa(temp_data15),.datab(temp_data15),.result(ly2));
  defparam lpm_multe2.lpm_widtha=11;
  defparam lpm_multe2.lpm_widthb=11;
  defparam lpm_multe2.lpm_widths=11;
  defparam lpm_multe2.lpm_widthp=22;
  defparam lpm_multe2.lpm_representation  = "SIGNED"; 

 lpm_add_sub lpm_add_sub3(.result(temp_wire3),.dataa(ly2),.datab(lv2));
   defparam lpm_add_sub3.lpm_width =22;
   defparam lpm_add_sub3.lpm_representation = "SIGNED";
   defparam lpm_add_sub3.lpm_direction  = "SUB" ;
   
always @(posedge clk)
   begin
     out_data1<=temp_wire1+temp_wire2;
     out_data2<=lv_temp;
     out_data3<=temp_wire3;
     out_data14<=temp_data14;
     out_data15<=temp_data15;
     
   end
  
   
endmodule