⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 filter.fnsim.qmsg

📁 图像处理技术中3*3模板的滤波电路的VHDL实现.
💻 QMSG
📖 第 1 页 / 共 2 页
字号:
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aset add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"aset\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sclr add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"sclr\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sset add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"sset\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aload add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"aload\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sload add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"sload\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aclr add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"aclr\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cin1 add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"cin1\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add_1p:add9\|lpm_add_sub:add_1 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add_1p:add9\|lpm_add_sub:add_1\"" {  } { { "add_1p .v" "add_1" { Text "F:/sopc/lunwen/filter/add_1p .v" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_1p:add9\|lpm_add_sub:add_1 " "Info: Elaborated megafunction instantiation \"add_1p:add9\|lpm_add_sub:add_1\"" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 40 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add_1p:add9\|lpm_add_sub:add_1 " "Info: Instantiated megafunction \"add_1p:add9\|lpm_add_sub:add_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 7 " "Info: Parameter \"lpm_width\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction add " "Info: Parameter \"lpm_direction\" = \"add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 40 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qjc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qjc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qjc " "Info: Found entity 1: add_sub_qjc" {  } { { "db/add_sub_qjc.tdf" "" { Text "F:/sopc/lunwen/filter/db/add_sub_qjc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_qjc add_1p:add9\|lpm_add_sub:add_1\|add_sub_qjc:auto_generated " "Info: Elaborating entity \"add_sub_qjc\" for hierarchy \"add_1p:add9\|lpm_add_sub:add_1\|add_sub_qjc:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ff add_1p:add9\|lpm_ff:reg_1 " "Info: Elaborating entity \"lpm_ff\" for hierarchy \"add_1p:add9\|lpm_ff:reg_1\"" {  } { { "add_1p .v" "reg_1" { Text "F:/sopc/lunwen/filter/add_1p .v" 48 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_1p:add9\|lpm_ff:reg_1 " "Info: Elaborated megafunction instantiation \"add_1p:add9\|lpm_ff:reg_1\"" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 48 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add_1p:add9\|lpm_ff:reg_1 " "Info: Instantiated megafunction \"add_1p:add9\|lpm_ff:reg_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 7 " "Info: Parameter \"lpm_width\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 48 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ff add_1p:add9\|lpm_ff:reg_2 " "Info: Elaborating entity \"lpm_ff\" for hierarchy \"add_1p:add9\|lpm_ff:reg_2\"" {  } { { "add_1p .v" "reg_2" { Text "F:/sopc/lunwen/filter/add_1p .v" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_1p:add9\|lpm_ff:reg_2 " "Info: Elaborated megafunction instantiation \"add_1p:add9\|lpm_ff:reg_2\"" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 54 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add_1p:add9\|lpm_ff:reg_2 " "Info: Instantiated megafunction \"add_1p:add9\|lpm_ff:reg_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 1 " "Info: Parameter \"lpm_width\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 54 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add_1p:add9\|lpm_add_sub:add_2 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add_1p:add9\|lpm_add_sub:add_2\"" {  } { { "add_1p .v" "add_2" { Text "F:/sopc/lunwen/filter/add_1p .v" 60 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_1p:add9\|lpm_add_sub:add_2 " "Info: Elaborated megafunction instantiation \"add_1p:add9\|lpm_add_sub:add_2\"" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 60 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add_1p:add9\|lpm_add_sub:add_2 " "Info: Instantiated megafunction \"add_1p:add9\|lpm_add_sub:add_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 2 " "Info: Parameter \"lpm_width\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction add " "Info: Parameter \"lpm_direction\" = \"add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 60 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ljc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ljc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ljc " "Info: Found entity 1: add_sub_ljc" {  } { { "db/add_sub_ljc.tdf" "" { Text "F:/sopc/lunwen/filter/db/add_sub_ljc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_ljc add_1p:add9\|lpm_add_sub:add_2\|add_sub_ljc:auto_generated " "Info: Elaborating entity \"add_sub_ljc\" for hierarchy \"add_1p:add9\|lpm_add_sub:add_2\|add_sub_ljc:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ff add_1p:add9\|lpm_ff:reg_3 " "Info: Elaborating entity \"lpm_ff\" for hierarchy \"add_1p:add9\|lpm_ff:reg_3\"" {  } { { "add_1p .v" "reg_3" { Text "F:/sopc/lunwen/filter/add_1p .v" 67 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_1p:add9\|lpm_ff:reg_3 " "Info: Elaborated megafunction instantiation \"add_1p:add9\|lpm_ff:reg_3\"" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 67 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add_1p:add9\|lpm_ff:reg_3 " "Info: Instantiated megafunction \"add_1p:add9\|lpm_ff:reg_3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 2 " "Info: Parameter \"lpm_width\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 67 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add_1p:add9\|lpm_add_sub:add_3 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add_1p:add9\|lpm_add_sub:add_3\"" {  } { { "add_1p .v" "add_3" { Text "F:/sopc/lunwen/filter/add_1p .v" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_1p:add9\|lpm_add_sub:add_3 " "Info: Elaborated megafunction instantiation \"add_1p:add9\|lpm_add_sub:add_3\"" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 84 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add_1p:add9\|lpm_add_sub:add_3 " "Info: Instantiated megafunction \"add_1p:add9\|lpm_add_sub:add_3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 2 " "Info: Parameter \"lpm_width\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction add " "Info: Parameter \"lpm_direction\" = \"add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 84 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_urc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_urc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_urc " "Info: Found entity 1: add_sub_urc" {  } { { "db/add_sub_urc.tdf" "" { Text "F:/sopc/lunwen/filter/db/add_sub_urc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_urc add_1p:add9\|lpm_add_sub:add_3\|add_sub_urc:auto_generated " "Info: Elaborating entity \"add_sub_urc\" for hierarchy \"add_1p:add9\|lpm_add_sub:add_3\|add_sub_urc:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 22 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "164 " "Info: Peak virtual memory: 164 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 23 19:25:42 2009 " "Info: Processing ended: Mon Feb 23 19:25:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -