shift_taps_c0m.tdf

图像处理技术中3*3模板的滤波电路的VHDL实现.

--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" NUMBER_OF_TAPS=1 TAP_DISTANCE=4 WIDTH=8 clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 8.1 cbx_altdpram 2008:05:19:10:27:12:SJ cbx_altshift_taps 2008:05:19:11:04:47:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ  VERSION_END


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FUNCTION altsyncram_e681 (address_a[0..0], address_b[0..0], clock0, clocken0, data_a[7..0], wren_a)
RETURNS ( q_b[7..0]);
FUNCTION cntr_ikf (clk_en, clock)
RETURNS ( q[0..0]);

--synthesis_resources = lut 1 M4K 1 reg 1 
SUBDESIGN shift_taps_c0m
( 
	clock	:	input;
	shiftin[7..0]	:	input;
	shiftout[7..0]	:	output;
	taps[7..0]	:	output;
) 
VARIABLE 
	altsyncram2 : altsyncram_e681;
	cntr1 : cntr_ikf;
	clken	: NODE;

BEGIN 
	altsyncram2.address_a[] = cntr1.q[];
	altsyncram2.address_b[] = cntr1.q[];
	altsyncram2.clock0 = clock;
	altsyncram2.clocken0 = clken;
	altsyncram2.data_a[] = ( shiftin[]);
	altsyncram2.wren_a = B"1";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	clken = VCC;
	shiftout[7..0] = altsyncram2.q_b[7..0];
	taps[] = altsyncram2.q_b[];
END;
--VALID FILE