filter.map.summary

图像处理技术中3*3模板的滤波电路的VHDL实现.

Analysis & Synthesis Status : Successful - Mon Feb 23 19:22:58 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Web Edition
Revision Name : filter
Top-level Entity Name : filter
Family : Cyclone II
Total logic elements : 106
    Total combinational functions : 26
    Dedicated logic registers : 106
Total registers : 106
Total pins : 19
Total virtual pins : 0
Total memory bits : 16
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0