filter.map.rpt

图像处理技术中3*3模板的滤波电路的VHDL实现.

; WIDTH          ; 8              ; Untyped                                                  ;
; POWER_UP_STATE ; CLEARED        ; Untyped                                                  ;
; CBXI_PARAMETER ; shift_taps_c0m ; Untyped                                                  ;
+----------------+----------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; altshift_taps Parameter Settings by Entity Instance                    ;
+----------------------------+-------------------------------------------+
; Name                       ; Value                                     ;
+----------------------------+-------------------------------------------+
; Number of entity instances ; 1                                         ;
; Entity Instance            ; reg8:reg8_23|altshift_taps:out_data_rtl_0 ;
;     -- NUMBER_OF_TAPS      ; 1                                         ;
;     -- TAP_DISTANCE        ; 4                                         ;
;     -- WIDTH               ; 8                                         ;
+----------------------------+-------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Mon Feb 23 19:22:49 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off filter -c filter
Info: Found 1 design units, including 1 entities, in source file reg8.v
    Info: Found entity 1: reg8
Info: Found 1 design units, including 1 entities, in source file filter.v
    Info: Found entity 1: filter
Info: Found 1 design units, including 1 entities, in source file count3.v
    Info: Found entity 1: count3
Info: Found 1 design units, including 1 entities, in source file add8_9.v
    Info: Found entity 1: add8_9
Info: Found 1 design units, including 1 entities, in source file add_1p .v
    Info: Found entity 1: add_1p
Info: Elaborating entity "filter" for the top level hierarchy
Info: Elaborating entity "reg8" for hierarchy "reg8:reg8_11"
Info: Elaborating entity "count3" for hierarchy "count3:count31"
Warning (10230): Verilog HDL assignment warning at count3.v(12): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at count3.v(15): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "add8_9" for hierarchy "add8_9:add8_91"
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object "clkena" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object "ADD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object "ena" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object "aset" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object "sclr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object "sset" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object "aload" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object "sload" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object "aclr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object "cin1" assigned a value but never read
Info: Elaborating entity "lpm_add_sub" for hierarchy "add8_9:add8_91|lpm_add_sub:add_1"
Info: Elaborated megafunction instantiation "add8_9:add8_91|lpm_add_sub:add_1"
Info: Instantiated megafunction "add8_9:add8_91|lpm_add_sub:add_1" with the following parameter:
    Info: Parameter "lpm_width" = "8"
    Info: Parameter "lpm_direction" = "add"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_rjc.tdf
    Info: Found entity 1: add_sub_rjc
Info: Elaborating entity "add_sub_rjc" for hierarchy "add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated"
Info: Elaborating entity "add_1p" for hierarchy "add_1p:add9"
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object "clkena" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object "ADD" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object "ena" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object "aset" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object "sclr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object "sset" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object "aload" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object "sload" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object "aclr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object "cin1" assigned a value but never read
Info: Elaborating entity "lpm_add_sub" for hierarchy "add_1p:add9|lpm_add_sub:add_1"
Info: Elaborated megafunction instantiation "add_1p:add9|lpm_add_sub:add_1"
Info: Instantiated megafunction "add_1p:add9|lpm_add_sub:add_1" with the following parameter:
    Info: Parameter "lpm_width" = "7"
    Info: Parameter "lpm_direction" = "add"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_qjc.tdf
    Info: Found entity 1: add_sub_qjc
Info: Elaborating entity "add_sub_qjc" for hierarchy "add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated"
Info: Elaborating entity "lpm_ff" for hierarchy "add_1p:add9|lpm_ff:reg_1"
Info: Elaborated megafunction instantiation "add_1p:add9|lpm_ff:reg_1"
Info: Instantiated megafunction "add_1p:add9|lpm_ff:reg_1" with the following parameter:
    Info: Parameter "lpm_width" = "7"
Info: Elaborating entity "lpm_ff" for hierarchy "add_1p:add9|lpm_ff:reg_2"
Info: Elaborated megafunction instantiation "add_1p:add9|lpm_ff:reg_2"
Info: Instantiated megafunction "add_1p:add9|lpm_ff:reg_2" with the following parameter:
    Info: Parameter "lpm_width" = "1"
Info: Elaborating entity "lpm_add_sub" for hierarchy "add_1p:add9|lpm_add_sub:add_2"
Info: Elaborated megafunction instantiation "add_1p:add9|lpm_add_sub:add_2"
Info: Instantiated megafunction "add_1p:add9|lpm_add_sub:add_2" with the following parameter:
    Info: Parameter "lpm_width" = "2"
    Info: Parameter "lpm_direction" = "add"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_ljc.tdf
    Info: Found entity 1: add_sub_ljc
Info: Elaborating entity "add_sub_ljc" for hierarchy "add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated"
Info: Elaborating entity "lpm_ff" for hierarchy "add_1p:add9|lpm_ff:reg_3"
Info: Elaborated megafunction instantiation "add_1p:add9|lpm_ff:reg_3"
Info: Instantiated megafunction "add_1p:add9|lpm_ff:reg_3" with the following parameter:
    Info: Parameter "lpm_width" = "2"
Info: Elaborating entity "lpm_add_sub" for hierarchy "add_1p:add9|lpm_add_sub:add_3"
Info: Elaborated megafunction instantiation "add_1p:add9|lpm_add_sub:add_3"
Info: Instantiated megafunction "add_1p:add9|lpm_add_sub:add_3" with the following parameter:
    Info: Parameter "lpm_width" = "2"
    Info: Parameter "lpm_direction" = "add"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_urc.tdf
    Info: Found entity 1: add_sub_urc
Info: Elaborating entity "add_sub_urc" for hierarchy "add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altshift_taps megafunction from the following design logic: "reg8:reg8_23|out_data[6]~8"
        Info: Parameter NUMBER_OF_TAPS set to 1
        Info: Parameter TAP_DISTANCE set to 4
        Info: Parameter WIDTH set to 8
Info: Elaborated megafunction instantiation "reg8:reg8_23|altshift_taps:out_data_rtl_0"
Info: Instantiated megafunction "reg8:reg8_23|altshift_taps:out_data_rtl_0" with the following parameter:
    Info: Parameter "NUMBER_OF_TAPS" = "1"
    Info: Parameter "TAP_DISTANCE" = "4"
    Info: Parameter "WIDTH" = "8"
Info: Found 1 design units, including 1 entities, in source file db/shift_taps_c0m.tdf
    Info: Found entity 1: shift_taps_c0m
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e681.tdf
    Info: Found entity 1: altsyncram_e681
Info: Found 1 design units, including 1 entities, in source file db/cntr_ikf.tdf
    Info: Found entity 1: cntr_ikf
Info: Implemented 134 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 10 output pins
    Info: Implemented 107 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
    Info: Peak virtual memory: 172 megabytes
    Info: Processing ended: Mon Feb 23 19:22:58 2009
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:07