count3.v

来自「图像处理技术中3*3模板的滤波电路的VHDL实现.」· Verilog 代码 · 共 16 行

module count3(out,cout,en,clr,clk);
output[1:0] out;
output cout;

input en,clr,clk;
reg[1:0] out;

always@(posedge clk or posedge clr)
begin if(clr) out<=0;
      else if(en)
           begin if(out==2) out<=0;
           else         out<=out+1;
           end
end
assign cout=((out==2)&en)?1:0;
endmodule