add8_9.v

来自「图像处理技术中3*3模板的滤波电路的VHDL实现.」· Verilog 代码 · 共 47 行

module add8_9 (x, y, sum, clk);  
  parameter WIDTH   = 8, // Total bit width
            WIDTH1  = 8;  // Bit width of LSBs 
        

  input [WIDTH-1:0] x,y;  // Inputs
  output [WIDTH:0] sum;  // Result
  input              clk;  // Clock

  reg  [WIDTH1-1:0] l1, l2; // LSBs of inputs
  wire [WIDTH1-1:0] q1, r1; // LSBs of inputs
  reg  [WIDTH:0]  s;    // Output register
  wire cr1,cq1; // LSBs carry signal
 // wire [WIDTH2-1:0] h2; // Auxiliary MSBs of input
     
  wire  clkena, ADD, ena, aset, sclr;  // Auxiliary signals
  wire sset, aload, sload, aclr, ovf1, cin1; 

// Default for add:
  assign cin1=0; assign aclr=0; assign ADD=1; 

  assign ena=1; assign aclr=0;            // Default for FF
  assign sclr=0; assign sset=0; assign aload=0; 
  assign sload=0; assign clkena=0; assign aset=0;

  // Split in MSBs and LSBs and store in registers
  always @(posedge clk) begin
    // Split LSBs from input x,y
    l1[WIDTH1-1:0] <= x[WIDTH1-1:0];
    l2[WIDTH1-1:0] <= y[WIDTH1-1:0];
  end
/************* First stage of the adder  *****************/
  lpm_add_sub add_1                  // Add LSBs of x and y
  ( .result(r1), .dataa(l1), .datab(l2), .cout(cr1)); 
                                              // Used ports
//  .overflow(ovl1), .clken(clkena), .add_sub(ADD),
//  .cin(cin1), .clock(clk), .aclr(aclr)); // Unused ports
    defparam add_1.lpm_width = WIDTH1;
    defparam add_1.lpm_direction = "add";

  always @(posedge clk) begin  // Build a single registered
    s = {cr1,r1[7:0]};     // output word 
  end                             // of WIDTH=WIDTH1+WIDTH2

  assign sum = s ;    // Connect s to output pins

endmodule