jpeg_d_package.v

来自「JPEG_D IP Core Verilog crypted source」· Verilog 代码 · 共 54 行

//---------------------------------------------------------------------------
// Project  : JPEG-D - Baseline JPEG Decoder
//
// File     : jpeg_d_package.v
//
// Purpose  : Package for JPEG Decoder core
//
// Created by ALMA Technologies S.A.
// Copyright (c) 2001-2007 Alma Technologies S.A.
//
//---------------------------------------------------------------------------
// Design Engineer        : S. Theoharis
// Quality Engineer       : G. Anagnostopoulos
// Creation Date          : 16 December 2002
// Last Modification Date : 21 November 2003
// File history           :
//      16 December 2002 (1.00)
//      21 November 2003 (2.00) : Updated file header to adhere company's template
//---------------------------------------------------------------------------
// Please review the terms of the license agreement before using this file.
// If you are not an authorized user, please destroy this source code file
// and notify Alma Technologies or CAST, Inc. immediately that you
// inadvertently received an unauthorized copy.
//---------------------------------------------------------------------------


//---------------------------------------------------------------
// What is the simulation timescale ?
//---------------------------------------------------------------
`timescale 1 ns / 1 ps

//---------------------------------------------------------------
// User defined constants that could be modified ...
//---------------------------------------------------------------
`define RESET_EDGE               posedge     // Change value to 'negedge' for logical low asynchronous reset
`define RESET_VALUE              1           // Change value to 0 for logical low asynchronous reset
`define NO_PIPELINED                         // NO_PIPELINED : non pipelined multipliers are used
                                             // PIPELINED1   : pipelined multipliers (small,slow)
                                             // PIPELINED2   : pipelined multipliers (large,fast)
`define HUFFMAND_PIPELINED_ARCH1             // Selects among different pipeline architectures in Huffman Decoder
                                             // (Suggested: HUFFMAND_PIPELINED_ARCH1 for FPGAs,
                                             //             HUFFMAND_PIPELINED_ARCH2 or HUFFMAND_PIPELINED_ARCH3 for ASICs)
`define DATA_HOLD                            // If DATA_HOLD : "Data-Hold" memories else if DATA_PIPE : "Data-Pipe" memories are used
`define HUFFMAND_FIFO_ADDR_BITS  8           // 2**`HUFFMAND_FIFO_ADDR_BITS words for Huffman Decoder's Output Stream FIFO
`define STREAM_FIFO_ADDR_BITS    7           // 2**`STREAM_FIFO_ADDR_BITS words for JPEG Input Stream FIFO

//---------------------------------------------------------------
// JPEG Baseline parameters : Don't change them ...
//---------------------------------------------------------------
`define N_FILTER_BITS 15                      // Number of bits for filter's data path.
`define N_FRAC_BITS   (`N_FILTER_BITS - 11)   // Number of bits for filter's float part.
`define N_INPUT_BITS  11                      // Number of bits for IDCT output samples.
`define N_OUTPUT_BITS 8                       // Number of bits for IDCT input coefficients.