jpeg_d.v

JPEG_D IP Core Verilog crypted source

// --------------------------------------------------------------------------
// Project  : JPEG-D - Baseline JPEG Decoder
//
// File     : jpeg_d.v
//
// Purpose  : JPEG Decoder's top level component
//
// Created by ALMA Technologies S.A.
// Copyright (c) 2001-2007 Alma Technologies S.A.
//
// --------------------------------------------------------------------------
// Design Engineer        : S. Theoharis, G. Anagnostopoulos
// Quality Engineer       : N. Zervas
// Creation Date          : 16 December 2002
// Last Modification Date : 21 November 2003
// File history           :
//      16 December 2002 (1.00)
//      13 January  2003 (1.01) : Corrected bugs concerning IF stall
//      21 November 2003 (2.00) : Updated file header to adhere company's template
// --------------------------------------------------------------------------
// Please review the terms of the license agreement before using this file.
// If you are not an authorized user, please destroy this source code file
// and notify Alma Technologies or CAST, Inc. immediately that you
// inadvertently received an unauthorized copy.
// --------------------------------------------------------------------------

`include "jpeg_d_package.v"

module jpeg_d (clk, clr, rst, enable, c_din, c_wen, s_dout, s_addr, s_ren, configerror, scanactive, soi, eoi, jpegin, jpegin_wen, jpegin_rdy, pixelout, pixelout_wen, pixelout_rdy, pixelout_sob, pixelout_eob, pixelout_lbs);

   // Global signals
   input clk;              // Global clock
   input clr;              // Synchronous clear
   input rst;              // Asynchronous reset
   input enable;           // Active high enable
   // Control Interface
   input[15:0] c_din;      // Control data
   input c_wen;            // Control write enable
   // Status Interface
   output[15:0] s_dout;    // Status data
   wire[15:0] s_dout;
   input[3:0] s_addr;      // Status read address
   input s_ren;            // Status read enable
   output configerror;     // Configuration Error
   wire configerror;
   output scanactive;      // Indicates that core encodes or decodes an entropy coded scan data
   wire scanactive;
   output soi;             // Indicates that a SOI marker has been output or detected
   wire soi;
   output eoi;             // Indicates that an EOI marker has been output or detected
   wire eoi;
   // Jpeg-In Interface
   input[7:0] jpegin;      // JPEG stream input data
   input jpegin_wen;       // JpegIN write enable: Masks JPEG stream input data
   output jpegin_rdy;      // JpegIn ready: Core is ready to accept new data on JpegIN
   wire jpegin_rdy;
   // Pixel-Out Interface
   output[7:0] pixelout;   // Pixel output data
   wire[7:0] pixelout;
   output pixelout_wen;    // Pixel output data write enable
   wire pixelout_wen;
   input pixelout_rdy;     // Pixel output data ready: Stalls pixel output interface
   output pixelout_sob;    // Pixel output start of block: Masks the 1st sample of each 8x8 block
   wire pixelout_sob;
   output pixelout_eob;    // Pixel output end of block: Mask the last sample of each 8x8 block
   wire pixelout_eob;
   output pixelout_lbs;    // Pixel output last block in scan: Masks all samples of the last 8x8 block
   wire pixelout_lbs;

   // Architecture declarations
   // Internal signal declarations
   wire[7:0] dqt_addr;                                         // Quantization Tables RAM address
   wire[7:0] dqt_din;                                          // Quantization Tables RAM data input
   wire[7:0] dqt_dout;                                         // Quantization Tables RAM data output
   wire dqt_ren;                                               // Quantization Tables RAM read enable
   wire dqt_wen;                                               // Quantization Tables RAM write enable
   wire[8:0] huffman_d_tables_addr;                            // Huffman Tables RAM address
   wire[7:0] huffman_d_tables_din;                             // Huffman Tables RAM data input
   wire[7:0] huffman_d_tables_dout;                            // Huffman Tables RAM data output
   wire huffman_d_tables_ren;                                  // Huffman Tables RAM read address
   wire huffman_d_tables_wen;                                  // Huffman Tables RAM write enable
   wire[10:0] idct_buffer_din;                                 // IDCT buffer RAM data input
   wire[10:0] idct_buffer_dout;                                // IDCT buffer RAM data output
   wire[6:0] idct_buffer_raddr;                                // IDCT buffer RAM read address
   wire idct_buffer_ren;                                       // IDCT buffer RAM read enable
   wire[6:0] idct_buffer_waddr;                                // IDCT buffer RAM write address
   wire idct_buffer_wen;                                       // IDCT buffer RAM write enable
   wire[`N_FILTER_BITS - 1:0] idct_transpose_din;              // IDCT transpose RAM data input
   wire[`N_FILTER_BITS - 1:0] idct_transpose_dout;             // IDCT transpose RAM data output
   wire[5:0] idct_transpose_raddr;                             // IDCT transpose RAM read address
   wire idct_transpose_ren;                                    // IDCT transpose RAM read enable
   wire[5:0] idct_transpose_waddr;                             // IDCT transpose RAM write address
   wire idct_transpose_wen;                                    // IDCT transpose RAM write enable
   wire[22:0] huffman_d_fifo_din;                              // Huffman Decoder's parameter/symbol fifo RAM data input
   wire[`HUFFMAND_FIFO_ADDR_BITS - 1:0] huffman_d_fifo_waddr;  // Huffman Decoder's parameter/symbol fifo RAM write address
   wire[`STREAM_FIFO_ADDR_BITS - 1:0] stream_fifo_raddr;       // JPEG stream fifo RAM read address
   wire huffman_d_fifo_wen;                                    // Huffman Decoder's parameter/symbol fifo RAM write enable
   wire[22:0] huffman_d_fifo_dout;                             // Huffman Decoder's parameter/symbol fifo RAM data output
   wire[7:0] stream_fifo_din;                                  // JPEG stream fifo RAM data input
   wire[`STREAM_FIFO_ADDR_BITS - 1:0] stream_fifo_waddr;       // JPEG stream fifo RAM write address
   wire[`HUFFMAND_FIFO_ADDR_BITS - 1:0] huffman_d_fifo_raddr;  // Huffman Decoder's parameter/symbol fifo RAM read address
   wire[7:0] stream_fifo_dout;                                 // JPEG stream fifo RAM data output
   wire huffman_d_fifo_ren;                                    // Huffman Decoder's parameter/symbol fifo RAM read enable
   wire stream_fifo_ren;                                       // JPEG stream fifo RAM read enable
   wire stream_fifo_wen;                                       // JPEG stream fifo RAM write enable

   // Instance port mappings.
   jpeg_d_no_mem
      u_jpeg_d_no_mem
      (
       .c_din(c_din),
       .c_wen(c_wen),
       .clk(clk),
       .clr(clr),
       .dqt_dout(dqt_dout),
       .enable(enable),
       .huffman_d_tables_dout(huffman_d_tables_dout),
       .huffman_d_fifo_dout(huffman_d_fifo_dout),
       .idct_buffer_dout(idct_buffer_dout),
       .idct_transpose_dout(idct_transpose_dout),
       .jpegin(jpegin),
       .jpegin_wen(jpegin_wen),
       .pixelout_rdy(pixelout_rdy),
       .rst(rst),
       .s_addr(s_addr),
       .s_ren(s_ren),
       .stream_fifo_dout(stream_fifo_dout),
       .configerror(configerror),
       .dqt_addr(dqt_addr),
       .dqt_din(dqt_din),
       .dqt_ren(dqt_ren),
       .dqt_wen(dqt_wen),
       .eoi(eoi),
       .huffman_d_tables_addr(huffman_d_tables_addr),
       .huffman_d_tables_din(huffman_d_tables_din),
       .huffman_d_tables_ren(huffman_d_tables_ren),
       .huffman_d_tables_wen(huffman_d_tables_wen),
       .huffman_d_fifo_din(huffman_d_fifo_din),
       .huffman_d_fifo_raddr(huffman_d_fifo_raddr),
       .huffman_d_fifo_ren(huffman_d_fifo_ren),
       .huffman_d_fifo_waddr(huffman_d_fifo_waddr),
       .huffman_d_fifo_wen(huffman_d_fifo_wen),
       .idct_buffer_din(idct_buffer_din),
       .idct_buffer_raddr(idct_buffer_raddr),
       .idct_buffer_ren(idct_buffer_ren),
       .idct_buffer_waddr(idct_buffer_waddr),
       .idct_buffer_wen(idct_buffer_wen),
       .idct_transpose_din(idct_transpose_din),
       .idct_transpose_raddr(idct_transpose_raddr),
       .idct_transpose_ren(idct_transpose_ren),
       .idct_transpose_waddr(idct_transpose_waddr),
       .idct_transpose_wen(idct_transpose_wen),
       .jpegin_rdy(jpegin_rdy),
       .pixelout(pixelout),
       .pixelout_eob(pixelout_eob),
       .pixelout_lbs(pixelout_lbs),
       .pixelout_sob(pixelout_sob),
       .pixelout_wen(pixelout_wen),
       .s_dout(s_dout),
       .scanactive(scanactive),
       .soi(soi),
       .stream_fifo_din(stream_fifo_din),
       .stream_fifo_raddr(stream_fifo_raddr),
       .stream_fifo_ren(stream_fifo_ren),
       .stream_fifo_waddr(stream_fifo_waddr),
       .stream_fifo_wen(stream_fifo_wen)
      );

   dqt_ram
      u_dqt_ram
      (
       .addr(dqt_addr),
       .clk(clk),
       .rd_en(dqt_ren),
       .rst(rst),
       .wr_data(dqt_din),
       .wr_en(dqt_wen),
       .rd_data(dqt_dout)
      );

   huffman_d_tables_ram
      u_huffman_d_tables_ram
      (
       .addr(huffman_d_tables_addr),
       .clk(clk),
       .rd_en(huffman_d_tables_ren),
       .rst(rst),
       .wr_data(huffman_d_tables_din),
       .wr_en(huffman_d_tables_wen),
       .rd_data(huffman_d_tables_dout)
      );

   huffman_d_fifo_ram #(`HUFFMAND_FIFO_ADDR_BITS)
      u_huffman_d_fifo_ram
      (
       .clk(clk),
       .rd_addr(huffman_d_fifo_raddr),
       .rd_en(huffman_d_fifo_ren),
       .rst(rst),
       .wr_addr(huffman_d_fifo_waddr),
       .wr_data(huffman_d_fifo_din),
       .wr_en(huffman_d_fifo_wen),
       .rd_data(huffman_d_fifo_dout)
      );

   idct_buffer_ram
      u_idct_buffer_ram
      (
       .clk(clk),
       .rd_addr(idct_buffer_raddr),
       .rd_en(idct_buffer_ren),
       .rst(rst),
       .wr_addr(idct_buffer_waddr),
       .wr_data(idct_buffer_din),
       .wr_en(idct_buffer_wen),
       .rd_data(idct_buffer_dout)
      );

   idct_transpose_ram
      u_idct_transpose_ram
      (
       .clk(clk),
       .rd_addr(idct_transpose_raddr),
       .rd_en(idct_transpose_ren),
       .rst(rst),
       .wr_addr(idct_transpose_waddr),
       .wr_data(idct_transpose_din),
       .wr_en(idct_transpose_wen),
       .rd_data(idct_transpose_dout)
      );

   stream_fifo_ram #(`STREAM_FIFO_ADDR_BITS)
      u_stream_fifo_ram
      (
       .clk(clk),
       .rd_addr(stream_fifo_raddr),
       .rd_en(stream_fifo_ren),
       .rst(rst),
       .wr_addr(stream_fifo_waddr),
       .wr_data(stream_fifo_din),
       .wr_en(stream_fifo_wen),
       .rd_data(stream_fifo_dout)
      );

endmodule